Machine intelligence and learning for graphic chip accessibility and execution
View Patent ↗Methods and systems enabling rapid application development, verification, and deployment requiring only knowledge of high level languages. Two aspects of the disclosed methods and systems are called Machine Intelligence and Learning for Graphic chip Accessibility (MILeGrA) and Machine Intelligence and Learning for Graphic chip Execution (MILeGrE). Using MILeGrA and MILeGrE, high-level language programmers do not need to learn complex coprocessor programming languages, but can still use coprocessors (e.g., GPU processors) to benefit from results-in-seconds big data capabilities through the translation of coprocessor-unaware code to coprocessor-aware code. Execution of such coprocessor-unaware code on coprocessors includes parsing the coprocessor-unaware code to generate intermediate code, analyzing the intermediate code to determine a model for coprocessor-aware code generation, and generating coprocessor-aware code based on the model using machine learning techniques.
1. A method of enabling execution of coprocessor-unaware computer code on coprocessors, the method comprising:
parsing coprocessor-unaware computer code to generate intermediate code;
analyzing the intermediate code to determine a model for coprocessor-aware computer code generation;
generating coprocessor-aware computer code based on the model using machine learning; and
compiling the coprocessor-aware computer code and executing the complied code.
2. A method as in claim 1 wherein the coprocessor-unaware computer code includes non-parallel computer code, and wherein the coprocessor-aware computer code includes thread safe and scalable parallel computer code.
3. A method as in claim 1 wherein generating coprocessor-aware computer code using machine learning includes using a neural network.
4. A method as in claim 3 further including training the neural network using samples of intermediate code and corresponding coprocessor-aware computer code.
5. A method as in claim 1 wherein the coprocessors are any of graphic processing units, field programmable gate arrays, accelerated processing units, and security layer processors.
6. A method as in claim 1 wherein the coprocessor-unaware computer code type is any of Matlab, Julia, Python, C, and Fortran programming languages, and wherein the coprocessor-aware computer code type is an OpenCL programming language.
7. A method as in claim 1 wherein analyzing the intermediate code includes determining a model for coprocessor-aware computer code generation based on training data including samples of intermediate code and corresponding models.
8. A method as in claim 1 wherein analyzing the intermediate code includes determining a numerical method, and wherein generating coprocessor-aware computer code includes generating coprocessor-aware computer code based on the model and the numerical method.
9. A method as in claim 1 further comprising:
testing link optimizations for the compiled code based on the model to determine optimal execution parameters and thread safety; and
wherein executing the complied code includes executing the complied code with the optimal execution parameters.
10. A method as in claim 1 further comprising:
probing physical interfaces to identify coprocessors;
loading device drivers corresponding to the coprocessors;
obtaining attributes of the coprocessors; and
creating a device network representation based on the device drivers and attributes of the coprocessors.
11. A method as in claim 10 further including storing the device drivers in an elastic database.
12. A method as in claim 10 wherein generating coprocessor-aware computer code includes generating coprocessor-aware computer code based on the device network representation.
13. A method of creating a representation of a device network having coprocessors, the method comprising:
probing physical interfaces to identify coprocessors;
loading device drivers corresponding to the coprocessors;
obtaining attributes of the coprocessors; and
creating a device network representation based on the device drivers and attributes of the coprocessors.
14. A method as in claim 13 wherein the representation of the device network includes any of a number and type of coprocessors in the network, a number and type of central processing units in the network, types of memory in the network, and memory available in central processing units or coprocessors of the network.
15. A system for executing coprocessor-unaware computer code on coprocessors, the system comprising:
a device network having coprocessors;
source code written in coprocessor-unaware computer code; and
a coprocessor-aware computer code generation program configured to (i) parse the source code to generate intermediate code, (ii) analyze the intermediate code to determine a model for coprocessor-aware computer code generation, (iii) generate coprocessor-aware computer code based on the model using machine learning; and (iv) execute the coprocessor-aware computer code using the coprocessors.
16. A system as in claim 15 wherein the coprocessor-unaware computer code includes non-parallel computer code, and wherein the coprocessor-aware computer code includes parallel thread safe and scalable computer code.
17. A system as in claim 15 wherein the coprocessor-aware computer code generation program generates coprocessor-aware computer code using a neural network.
18. A system as in claim 17 wherein the neural network is trained using samples of intermediate code and corresponding coprocessor-aware computer code.
19. A system as in claim 15 wherein the coprocessors are any of graphic processing units, field programmable gate arrays, accelerated processing units, and security layer processors.
20. A system as in claim 15 wherein the coprocessor-unaware computer code type is any of Matlab, Julia, Python, C, and Fortran programming languages, and wherein the coprocessor-aware computer code type is an OpenCL programming language.
21. A system as in claim 15 wherein the coprocessor-aware computer code generation program determines a model for coprocessor-aware computer code generation based on training data including samples of intermediate code and corresponding models.
22. A system as in claim 15 wherein the coprocessor-aware computer code generation program determines a numerical method for the intermediate code and generates the coprocessor-aware computer code based on the numerical method.
23. A system as in claim 15 further comprising:
physical interfaces to the coprocessors;
an elastic database; and
a coprocessor discovery program configured to (i) probe the physical interfaces to identify the coprocessors, (ii) load, from the elastic database, device drivers corresponding to the coprocessors, (iii) obtain attributes of the coprocessors, and (iv) create a device network representation based on the device drivers and attributes of the coprocessors.
24. A system as in claim 23 wherein the coprocessor-aware computer code generation program generates the coprocessor-aware computer code based on the device network representation.
25. A machine readable storage medium having stored thereon a computer program for enabling execution of coprocessor-unaware computer code on coprocessors, the computer program comprising a routine of set instructions for causing the machine to:
parse coprocessor-unaware computer code to generate intermediate code;
analyze the intermediate code to determine a model for coprocessor-aware computer code generation; and
generate coprocessor-aware computer code based on the model and using machine learning; and
compile the coprocessor-aware computer code and execute the complied code.