Semiconductor memory device
View Patent ↗In a semiconductor memory device of an embodiment, a write circuit includes an inversion circuit configured to invert write data and output the inverted write data, a first switch configured to pass or stop a current for programming a first memory cell in the first memory cell array to a selected bit line of the first memory cell array, a second switch configured to pass or stop a current for programming a second memory cell in the second memory cell array to a selected bit line of the second memory cell array, and a gate circuit configured to program one of the first memory cell and the second memory cell, and unprogram another of the first memory cell and the second memory cell simultaneously, by controlling the first switch based on the write data and controlling the second switch based on the inverted write data.
1. A semiconductor memory device of a multi-block configuration that controls reading and writing of respective memory cells of first and second memory cell arrays by a common readout circuit and write circuit,
wherein the write circuit comprises
an inversion circuit configured by an EXOR circuit that obtains exclusive OR of write data and a signal indicating a test mode, the inversion circuit being further configured to invert the write data at a time of the test mode and output the inverted write data;
a first switch configured to pass or stop a current for programming a first memory cell in the first memory cell array to a selected bit line of the first memory cell array;
a second switch configured to pass or stop a current for programming a second memory cell in the second memory cell array to a selected bit line of the second memory cell array; and
a gate circuit configured to program one of the first memory cell and the second memory cell, and unprogram another of the first memory cell and the second memory cell simultaneously, by controlling the first switch based on the write data and controlling the second switch based on the inverted write data,
wherein the gate circuit comprises a first NAND circuit configured to control the first switch based on a signal indicating a test mode and the write data, and a second NAND circuit configured to control the second switch based on the signal indicating the test mode and the inverted write data.
2. The semiconductor memory device according to claim 1 ,
wherein the first and second memory cell arrays are configured by nonvolatile memory cells.
3. The semiconductor memory device according to claim 1 ,
wherein the first and second memory cell arrays are NOR-type flash memory cells.
4. The semiconductor memory device according to claim 1 ,
wherein the test mode is for performing writing of a diagonal pattern.
5. A semiconductor memory device of a multi-block configuration that controls reading and writing of respective memory cells of first and second memory cell arrays by a common readout circuit and write circuit,
wherein the write circuit comprises
an inversion circuit configured by an EXOR circuit that obtains exclusive OR of write data and a signal indicating a test mode, the inversion circuit being further configured to invert the write data at a time of the test mode and output the inverted write data;
a first switch configured to pass or stop a current for programming a first memory cell in the first memory cell array to a selected bit line of the first memory cell array;
a second switch configured to pass or stop a current for programming a second memory cell in the second memory cell array to a selected bit line of the second memory cell array; and
a gate circuit configured to program one of the first memory cell and the second memory cell, and unprogram another of the first memory cell and the second memory cell simultaneously, by controlling the first switch based on the write data and controlling the second switch based on the inverted write data,
wherein the gate circuit comprises a first AND circuit configured to control the first switch based on a signal indicating a test mode and the write data, and a second AND circuit configured to control the second switch based on the signal indicating the test mode and the inverted write data.
6. The semiconductor memory device according to claim 5 , wherein the first and second memory cell arrays are configured by nonvolatile memory cells.
7. The semiconductor memory device according to claim 5 , wherein the first and second memory cell arrays are NOR-type flash memory cells.
8. The semiconductor memory device according to claim 5 , wherein the test mode is for performing writing of a diagonal pattern.