Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices
III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.
1. A semiconductor heterostructure, comprising:
a substrate material with cubic crystallinity;
an elevated structure with hexagonal crystallinity in one or more trenches in a trench material, wherein the trench material is in contact with a crystal plane of the substrate material, and wherein the elevated structure has a c-plane substantially parallel to the crystal plane of the substrate material; and
wherein the elevated structure has inclined sidewall facets sloping from a top surface of the elevated structure to a location over the trench material and laterally beyond a sidewall of one or more trenches.
2. The semiconductor heterostructure of claim 1 , wherein:
the inclined sidewall facets are semi-polar planes intersecting the c-plane at angles of 50-80 degrees.
3. The semiconductor heterostructure of claim 2 , wherein at least one of the inclined sidewall facets is {1-101}, {11-22}, or {20-21} plane.
4. The semiconductor heterostructure of claim 1 , wherein:
the one or more trenches further comprise a first trench and a second trench; and
the elevated structure has a top surface substantially parallel with the c-plane and extending between the first and second trench.
5. The semiconductor heterostructure of claim 4 , further comprising a plurality of threading dislocations extending from the crystal plane of the substrate material, through a z-height of the one or more trenches and bending toward one of the inclined sidewall facets.
6. The semiconductor heterostructure of claim 5 , wherein:
the plurality of threading dislocations further comprises a first threading dislocation proximal a sidewall of the one or more trenches and a second threading dislocation proximal a centerline of the one or more trenches; and
the first threading dislocation bends toward one of the inclined sidewall facets at a first z-height relative to the substrate material that is smaller than a second z-height at which the second threading dislocation bends toward one of the inclined sidewall facets.
7. The semiconductor heterostructure of claim 6 , wherein at least one of the inclined sidewall facets has a defect density that is at least an order of magnitude greater than the top surface of the elevated structure.
8. The semiconductor heterostructure of claim 1 , wherein:
the one or more trenches further comprises a first trench and a second trench; and
the elevated structure further comprises:
a first elevated structure disposed in the first trench with the c-plane no more than 10° from parallel to a (100) plane of the substrate material and having first inclined sidewall facets intersecting the c-plane at angles of 50-80 degrees; and
a second elevated structure disposed in the second trench with the c-plane no more than 10° from parallel to a (100) plane of the substrate material and having second inclined sidewall facets intersecting the c-plane at angles of 50-80 degrees.
9. The semiconductor heterostructure of claim 8 , wherein:
the first inclined sidewall facets intersect each other, and the second inclined sidewall facets intersect each other; or wherein:
the first inclined sidewall facets are separated by a first top surface substantially parallel with the c-plane and the second inclined sidewall facets are separated by a second top surface substantially parallel with the c-plane.
10. The semiconductor heterostructure of claim 9 , wherein the first and second elevated structures have a z-height above a top surface of the trench material that is at least
3
2
times a lateral width of the first and second trenches, respectively.
11. The semiconductor heterostructure of claim 9 , wherein the first and second elevated structures have a z-height above a top surface of the trench material that is less than
3
2
times a lateral width of the first and second trenches, respectively, summed with a third of the pitch of the first and second trenches.
12. The semiconductor heterostructure of claim 1 , wherein the one or more trenches are first trenches, and further comprising:
a pair of second trenches exposing a surface of the elevated structure and with each of the second trenches over the first trenches, and laterally aligned between a pair of the first trenches; and
a cap having hexagonal crystallinity within the pair of second trenches and extending laterally over sidewalls of the pair of second trenches.
13. The semiconductor heterostructure of claim 1 , wherein:
the substrate material comprises (100) silicon; and
the one or more trenches extend over the substrate in the <110> direction, and individual ones of the one or more trenches have a lateral width no more than 500 nm.
14. A semiconductor device, comprising:
a heterostructure including:
a substrate material with cubic crystallinity;
an elevated structure with hexagonal crystallinity in one or more trenches of a trench material, and over a surface of the substrate material, wherein the elevated structure comprises a III-N material with the c-plane no more than 10° from parallel of a (100) plane of the substrate material, and wherein the one or more trenches have a longest length in a <110> direction of the substrate material, wherein the elevated structure has inclined sidewall facets sloping from a top surface of the elevated structure to an interface with the trench material laterally beyond a sidewall of the one or more trenches;
one or more device layers over a top surface of the elevated structure separating the inclined sidewall facets;
one or more device terminals coupled to the one or more device layers; and
a MOSFET over the substrate material adjacent to the elevated structure, wherein the MOSFET includes a source and a drain with a gate electrode therebetween, wherein the source and the drain are coupled through a channel length of the substrate material that extends in the <110> direction.
15. The semiconductor device of claim 14 , wherein:
the one or more device layers comprises a III-N polarization layer having a different composition than the elevated structure;
a gate stack comprising a first of the one or more device terminals is over the III-N polarization layer and a channel region of the elevated structure; and
a source terminal and a drain terminal are on opposite sides of the gate stack.
16. The semiconductor device of claim 15 , wherein:
the inclined sidewall facets are semi-polar planes intersecting the c-plane at angles of 50-80 degrees;
the gate stack, the source terminal, and the drain terminal are each over the top surface of the elevated structure parallel to the c-plane and extending between the inclined sidewall facets or extending in the <110> direction.