Semiconductor packages and methods of fabrication thereof
In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
1. A semiconductor device comprising:
a conductive substrate;
a first semiconductor chip disposed over the conductive substrate, the first semiconductor chip having a first side and an opposite second side;
a first chip contact pad disposed on the first side of the first semiconductor chip;
a second chip contact pad disposed on the second side of the first semiconductor chip, the second chip contact pad facing the conductive substrate;
a dielectric liner disposed over the first semiconductor chip, the dielectric liner comprising a plurality of first openings over the first chip contact pad;
an encapsulant disposed around the first semiconductor chip, wherein at least a portion of the encapsulant is in direct contact with the first side of the first semiconductor chip; and
a first interconnect contacting the first semiconductor chip through the plurality of first openings at the first chip contact pad, the first interconnect disposed in the encapsulant.
2. The device of claim 1 , further comprising:
a third chip contact pad disposed on the first side of the first semiconductor chip;
a plurality of second openings disposed in the dielectric liner over the third chip contact pad; and
a second interconnect contacting the first semiconductor chip through the plurality of second openings at the third chip contact pad.
3. The device of claim 1 , further comprising:
a second semiconductor chip, the second semiconductor chip having a first side and an opposite second side;
a third chip contact pad disposed on the first side of the second semiconductor chip, wherein the dielectric liner is disposed over the second chip, and wherein the dielectric liner comprises a plurality of second openings over the third chip contact pad; and
a second interconnect contacting the second semiconductor chip through the plurality of second openings at the third chip contact pad.
4. The device of claim 3 , wherein the second semiconductor chip is disposed over the conductive substrate.
5. The device of claim 1 , further comprising a solder or an adhesive glue disposed between the conductive substrate and the first semiconductor chip.
6. The device of claim 1 , wherein the conductive substrate is a die paddle of a leadframe.
7. A semiconductor device comprising:
a conductive substrate;
a first semiconductor chip having a first side and an opposite second side, the first semiconductor chip having a first chip contact pad on the first side and the second side being disposed over the conductive substrate,
wherein the first chip contact pad is disposed in a dielectric layer of an uppermost metal level of the first semiconductor chip, the first chip contact pad comprising a plurality of metallic segments that are electrically interconnected and disposed in the dielectric layer, and wherein the plurality of metallic segments is separated by a plurality of first openings in the first chip contact pad;
an encapsulant disposed over the first semiconductor chip, wherein at least a portion of the encapsulant is in direct contact with the first side of the first semiconductor chip; and
an interconnect disposed through the encapsulant and the openings of the first chip contact pad.
8. The device of claim 7 , further comprising:
a second chip contact pad disposed on the first side of the first semiconductor chip;
a plurality of second openings disposed at the second chip contact pad; and
a second interconnect contacting the first semiconductor chip through the plurality of second openings at the second chip contact pad.
9. The device of claim 7 , further comprising:
a second semiconductor chip having a first side and an opposite second side;
a second chip contact pad disposed on the first side of the second semiconductor chip; and
a second interconnect contacting the second semiconductor chip through a plurality of second openings at the second chip contact pad.
10. The device of claim 9 , wherein the second semiconductor chip is disposed over the conductive substrate.
11. The device of claim 7 , further comprising spacers disposed around sidewalls of the plurality of first openings of the first chip contact pad.
12. The device of claim 7 , wherein the plurality of metallic segments is coupled to an underlying metal line through a via.
13. The device of claim 7 , further comprising spacers disposed on sidewalls of the plurality of metallic segments.
14. The device of claim 13 , wherein the spacers comprise the same material as the encapsulant.
15. A semiconductor device comprising:
a first semiconductor chip having a first side and an opposite second side, the first semiconductor chip having a first chip contact pad on the first side,
wherein the first chip contact pad comprises a plurality of recesses below an upper surface of the first semiconductor chip;
a dielectric liner disposed over the first semiconductor chip, the dielectric liner contacting the first semiconductor chip, the dielectric liner comprising a plurality of segments alternating with a plurality of openings;
an encapsulant disposed over the first semiconductor chip;
an opening in the encapsulant and extending to the plurality of recesses; and
a conductive material disposed in the opening in the encapsulant and the plurality of openings in the dielectric liner.
16. The device of claim 15 , wherein each of the plurality of openings partially overlaps with a corresponding one of the plurality of recesses.
17. The device of claim 15 , wherein each of the plurality of recesses extends partially under the dielectric liner.
18. The device of claim 15 , further comprising an imide layer disposed between the dielectric liner and the encapsulant.
19. The device of claim 15 , further comprising an insulating layer disposed under a portion of the dielectric liner not overlapping with the first chip contact pad.
20. A semiconductor device comprising:
a conductive substrate;
a first semiconductor chip having a first side and an opposite second side, the first semiconductor chip having a first chip contact pad on the first side and the second side facing the conductive substrate;
a first chip contact pad disposed within a dielectric layer of an uppermost metal level of the first semiconductor chip, the first chip contact pad comprising a plurality of metallic segments that are electrically interconnected and disposed within the dielectric layer, and wherein the plurality of metallic segments is separated by openings in the first chip contact pad, wherein the plurality of metallic segments comprise a metallic top surface and sidewalls covered with an insulating sidewall spacer;
an encapsulant over the first semiconductor chip;
an opening in the encapsulant to expose the metallic top surface and the insulating sidewall spacer; and
a conductive material disposed in the opening in the encapsulant and the openings of the first chip contact pad, wherein the conductive material covers the metallic top surface and the insulating sidewall spacer.
21. The device of claim 20 , wherein the conductive material contacts the first chip contact pad through gaps between adjacent segments of the plurality of segments.
22. The device of claim 20 , further comprising a plurality of vias disposed under the plurality of metallic segments, wherein each of the plurality of metallic segments contacts one of the plurality of vias.