Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A source and drain region is positioned at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. The transistor includes a plurality of internal spacers, each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
1. A field effect transistor, comprising:
a stack of nanosheets of vertically arranged channel layers;
a source and drain region at respective ends of the vertically arranged channel layers;
a gate stack formed over, around, and between the vertically arranged channel layers; and
a plurality of internal spacers, each formed between the gate stack and a respective source or drain region, with at least one top pair of spacers being positioned above an uppermost channel layer, the top pair of spacers each comprising a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
2. The field effect transistor of claim 1 , wherein the source and drain regions each comprise a respective merged source or drain region that contacts multiple channel layers.
3. The field effect transistor of claim 2 , wherein the merged source and drain regions share a crystalline structure with the channel layers.
4. The field effect transistor of claim 3 , wherein the each merged source and drain region is epitaxially grown from a respective set of ends of the channel layers.
5. The field effect transistor of claim 1 , wherein the internal spacers each have a crescent shape.
6. The field effect transistor of claim 5 , wherein the source and drain regions have bulges complementary to recesses in the crescent-shaped internal spacers.
7. The field effect transistor of claim 5 , wherein the gate stack is recessed to accommodate a crescent shape of the topmost pair of inner spacers.
8. The field effect transistor of claim 1 , further comprising vestigial source and drain regions formed in lateral gate stacks on each side of the gate stack.
9. The field effect transistor of claim 1 , wherein the straight portion of the top pair of inner spacers extends along a sidewall of the gate stack.
10. The field effect transistor of claim 1 , wherein each nanosheet has a cross-sectional width that is significantly greater than a cross-sectional height.
11. A field effect transistor, comprising:
a stack of nanosheets of vertically arranged channel layers;
merged source and drain regions at respective ends of the vertically arranged channel layers, wherein each merged source and drain region contacts multiple channel layers;
a gate stack formed over, around, and between the vertically arranged channel layers; and
a plurality of crescent-shaped internal spacers, each formed between the gate stack and a respective source or drain region;
a pair of top spacers positioned above an uppermost channel layer, each comprising a crescent-shaped lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
12. The field effect transistor of claim 11 , wherein the merged source and drain regions share a crystalline structure with the channel layers.
13. The field effect transistor of claim 12 , wherein the each merged source and drain region is epitaxially grown from a respective set of ends of the channel layers.
14. The field effect transistor of claim 13 , wherein the source and drain regions have bulges complementary to recesses in the crescent-shaped internal spacers.
15. The field effect transistor of claim 13 , wherein the gate stack is recessed to accommodate a crescent shape of the topmost pair of inner spacers.
16. The field effect transistor of claim 11 , further comprising vestigial source and drain regions formed in lateral gate stacks on each side of the gate stack.
17. The field effect transistor of claim 11 , wherein the straight portion of the top pair of spacers extends along a sidewall of the gate stack.
18. The field effect transistor of claim 11 , wherein each nanosheet has a cross-sectional width that is significantly greater than a cross-sectional height.
19. A field effect transistor, comprising:
a stack of nanosheets of vertically arranged channel layers;
merged source and drain regions at respective ends of the vertically arranged channel layers that are epitaxially grown from and share a crystalline structure with respective ends of the channel layers, wherein each merged source and drain region contacts multiple channel layers;
a gate stack formed over, around, and between the vertically arranged channel layers;
a plurality of crescent-shaped internal spacers, each formed between the gate stack and a respective source or drain region, wherein the source and drain regions have bulges complementary to recesses in the crescent-shaped internal spacers and wherein the gate stack is recessed to accommodate a crescent shape of a topmost pair of inner spacers; and
a pair of top spacers positioned above an uppermost channel layer, each comprising a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
20. The field effect transistor of claim 19 , further comprising vestigial source and drain regions formed in lateral gate stacks on each side of the gate stack.