Tracking stores and loads by bypassing load store units
A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.
1. A method for tracking stores and loads to reduce load latency when storing and loading from a same memory address by bypassing a load store (LS) unit within an execution unit, the method comprising:
storing data in one or more memory dependent architectural register numbers (MdArns);
allocating the one or more MdArns to an in-memory file cache;
writing the allocated one or more MdArns to a file, wherein the file contains a MdArn map to enable subsequent access to an entry in the in-memory file cache;
upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the file to identify, via the one or more MdArns, an entry in the in-memory file cache and an associated store; and
on a hit, providing the entry responsive to the load request from the one or more MdArns by bypassing the LS unit.
2. The method of claim 1 further comprising allocating a free destination in a physical register file (PRF).
3. The method of claim 1 further comprising on a hit, preventing the LS unit from returning data responsive to load request.
4. The method of claim 1 wherein the preventing occurs in a scheduler.
5. The method of claim 4 wherein the scheduler comprises an arithmetic logic unit (ALU) scheduler (ALSQ).
6. The method of claim 4 wherein the scheduler comprises an address generation unit (AGU) scheduler (AGSQ).
7. A system for tracking stores and loads to reduce load latency when storing and loading from a same memory address by bypassing a load store (LS) unit within an execution unit, the system comprising:
a plurality of memory dependent architectural register numbers (MdArns) for storing data;
an in-memory file cache for allocating the at least one of the plurality of MdArns; and
a file for writing a MdArn map;
wherein upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the file to identify, via the plurality of MdArns, an entry in the in-memory file cache and an associated store; and
wherein on a hit, providing the entry responsive to the load request from the at least one of the plurality of MdArns by bypassing the LS unit.
8. The system of claim 7 further comprising a physical register file (PRF) to allocate a free destination.
9. The system of claim 7 further comprising on a hit, preventing the LS unit from returning data responsive to load request.
10. The system of claim 9 wherein the preventing is performed by a scheduler.
11. The system of claim 10 wherein the scheduler comprises an arithmetic logic unit (ALU) scheduler (ALSQ).
12. The system of claim 10 wherein the scheduler comprises an address generation unit (AGU) scheduler (AGSQ).
13. The system of claim 7 wherein the checking is performed by a scheduler and/or execution unit.
14. A non-transient computer readable medium containing program instructions for causing a computer to perform tracking stores and loads to reduce load latency when storing and loading from a same memory address by bypassing a load store (LS) unit within an execution unit, the method comprising:
storing data in one or more memory dependent architectural register numbers (MdArns);
allocating the one or more MdArns in an in-memory file cache;
writing the allocated one or more MdArns to a file, wherein the file contains a MdArn map to enable subsequent access to an entry in the in-memory file cache;
upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the file to identify, via the one or more MdArns, an entry in the in-memory file cache and an associated store; and
on a hit, providing the entry responsive to the load request from the one or more MdArns by bypassing the LS unit.
15. The computer readable medium of claim 14 , the method further comprising allocating a free destination in a physical register file (PRF).
16. The computer readable medium of claim 14 , the method further comprising on a hit, preventing the LS unit from returning data responsive to load request.
17. The computer readable medium of claim 16 wherein the preventing is performed by a scheduler.
18. The computer readable medium of claim 17 wherein the scheduler comprises an arithmetic logic unit (ALU) scheduler (ALSQ).
19. The computer readable medium of claim 17 wherein the scheduler comprises an address generation unit (AGU) scheduler (AGSQ).
20. The computer readable medium of claim 14 wherein the checking is performed by a scheduler and/or execution unit.