Methods for reducing dual damascene distortion

1. An integrated circuit structure comprising:

a first low-k dielectric layer having a first k value;

a transition layer overlying the first low-k dielectric layer, wherein the transition layer has a second k value lower than the first k value, wherein the second k value is substantially uniform in the transition layer;

a second low-k dielectric layer overlying the transition layer, the second low-k dielectric layer having a third k value lower than the second k value, wherein at an interface between the transition layer and the second low-k dielectric layer, there is an abrupt difference in k values of the transition layer and the second low-k dielectric layer; and

a dual damascene structure in the first low-k dielectric layer, the transition layer, and the second low-k dielectric layer.

2. The integrated circuit structure of claim 1 , wherein an entirety of the transition layer has the second k value that is substantially uniform.

3. The integrated circuit structure of claim 1 , wherein each of the first low-k dielectric layer, the second low-k dielectric layer, and the transition layer comprises silicon, carbon, and oxygen.

4. The integrated circuit structure of claim 3 , wherein the first low-k dielectric layer, the second low-k dielectric layer, and the transition layer have substantially equal percentages of silicon, carbon, and oxygen.

5. The integrated circuit structure of claim 1 , wherein the transition layer is more porous than the first low-k dielectric layer, and less porous than the second low-k dielectric layer.

6. The integrated circuit structure of claim 1 , wherein the dual damascene structure comprises a metal line extending into the second low-k dielectric layer, and a via extending into the first low-k dielectric layer.

7. The integrated circuit structure of claim 1 , wherein at an interface between the transition layer and the first low-k dielectric layer, there is an abrupt difference in k values of the transition layer and the first low-k dielectric layer.

8. The integrated circuit structure of claim 1 , wherein the dual damascene structure comprises a via and a metal line overlying the via, and the metal line has a bottom surface at an intermediate level between a top surface and a bottom surface of the transition layer.

9. The integrated circuit structure of claim 1 , wherein each of the first low-k dielectric layer and the second low-k dielectric layer has a uniform k value.

10. An integrated circuit structure comprising:

a first low-k dielectric layer having a first k value, wherein k values of an entirety of the first low-k dielectric layer are substantially uniform;

a transition layer overlying and contacting the first low-k dielectric layer, wherein the transition layer comprises a plurality of sub-layers, each having a k value different from k values in other ones of the plurality of sub-layers, wherein the k value in each of the plurality of subs-layers is substantially uniform;

a second low-k dielectric layer overlying and contacting the transition layer, wherein the second low-k dielectric layer has a second k value lower than k values of the plurality of sub-layers; and

a dual damascene structure comprising: a via comprising a portion in the first low-k dielectric layer; and

a metal line over and joined to the via, wherein the metal line comprises a portion in the second low-k dielectric layer.

11. The integrated circuit structure of claim 10 , wherein upper layers in the plurality of sub-layers have k values lower than respective lower layers in the plurality of sub-layers.

12. The integrated circuit structure of claim 10 , wherein each of the plurality of sub-layers has a substantially uniform k value.

13. The integrated circuit structure of claim 10 , wherein the metal line has a bottom surface level with or lower than a top surface of the transition layer.

14. The integrated circuit structure of claim 10 , wherein k values of the transition layer are lower than the first k value.

15. The integrated circuit structure of claim 10 , wherein at an interface between the transition layer and the second low-k dielectric layer, there is an abrupt difference between k values of the transition layer and the second low-k dielectric layer.

16. The integrated circuit structure of claim 15 , wherein there is an abrupt difference between k values of the transition layer and the first low-k dielectric layer.

17. An integrated circuit structure comprising:

a first low-k dielectric layer having a first k value;

a transition layer overlying the first low-k dielectric layer, wherein the transition layer has a second k value lower than the first k value, wherein the second k value is substantially uniform in the transition layer;

a second low-k dielectric layer overlying the transition layer, the second low-k dielectric layer having a third k value lower than the second k value, wherein at an interface between the first low-k dielectric layer and the transition layer, there is an abrupt in k values; and

a dual damascene structure in the first low-k dielectric layer, the transition layer, and the second low-k dielectric layer.

18. The integrated circuit structure of claim 17 , wherein an entirety of the transition layer has the third k value that is substantially uniform.

19. The integrated circuit structure of claim 17 , wherein the transition layer comprises a plurality of sub-layers, each having a k value different from k values in other ones of the plurality of sub-layer.

20. The integrated circuit structure of claim 19 , wherein upper layers in the plurality of sub-layers have k values lower than respective lower layers in the plurality of sub-layers.