Device with reinforced metal gate spacer and method of fabricating
A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
1. A semiconductor device comprising:
a substrate;
a gate structure on a channel portion of the substrate;
two gate spacers adjacent to two sides of the gate structure;
a first high-k dielectric material layer directly on an upper surface of the gate spacers;
a second high-k dielectric material layer directly on an upper surface of the gate structure; and
a mask material layer disposed directly on the second high-k dielectric layer, wherein a top surface of the first high-k dielectric material layer is leveled with a top surface of the mask material layer, and the mask material layer comprising a dielectric material being different from that of the first high-k dielectric material layer and the second high-k dielectric material layer and the first high-k dielectric material layer and the second high-k dielectric material layer comprising a same dielectric material.
2. The semiconductor device of claim 1 , wherein the mask material layer is within inner sidewalls of the first high-k dielectric material layer.
3. The semiconductor device of claim 2 , wherein a bottom surface of the first high-k dielectric material is higher than a bottom surface of the second high-k dielectric material.
4. The semiconductor device of claim 2 , wherein a bottom surface of the first high-k dielectric material layer is lower than a bottom surface of the second high-k dielectric material layer.
5. The semiconductor device of claim 2 , wherein a bottom surface of the first high-k dielectric material is level to a bottom surface of the second high-k dielectric material.
6. The semiconductor device of claim 1 , wherein the upper surface of the gate spacers is higher than the upper surface of the gate structure.
7. The semiconductor device of claim 6 , further comprising a self-aligned contact structure directly contacting a sidewall of the first high-k dielectric material.
8. The semiconductor device of claim 1 , wherein the upper surface of the gate spacers is lower than the upper surface of the gate structure.
9. The semiconductor device of claim 8 , further comprising a self-aligned contact structure directly contacting the first high-k dielectric material layer.
10. The semiconductor device of claim 1 , wherein the upper surface of the gate spacers is level to the upper surface of the gate structure.
11. The semiconductor device of claim 10 , further comprising a self-aligned contact structure directly contacting a sidewall of the first high-k dielectric material.
12. The semiconductor device of claim 1 , further comprising a self-aligned contact structure directly contacting the first high-k dielectric material layer.
13. The semiconductor device of claim 1 , further comprising an etch stop layer directly contacting a sidewall of the first high-k dielectric material layer.
14. The semiconductor device of claim 13 , wherein a bottom surface of the etch stop layer is level to a bottom surface of the second high-k dielectric material.
15. The semiconductor device of claim 13 , further comprising a self-aligned contact structure directly contacting a sidewall of the etch stop layer.