Embedded charge pump voltage regulator

1. A voltage regulator, comprising:

a power field effect transistor (FET) comprising a gate terminal;

a charge pump, the charge pump comprising a capacitor switchably coupled to the gate terminal; and

a current outputting amplifier coupled to a current source switchably coupled to the capacitor, wherein the capacitor is switchably coupled to a voltage source separately from the current outputting amplifier, wherein the current outputting amplifier is separate from the voltage source,

wherein the capacitor is switchably coupled to an operational transconductor via a current-to-voltage converter and a summer separately from the current outputting amplifier and the voltage source,

wherein the operational transconductor is separate from the current outputting amplifier and the voltage source, and

wherein an input of the operational transconductor is coupled to an output of the current outputting amplifier.

2. The voltage regulator of claim 1 , further comprising:

a first switch and a second switch connected in series; and

a third switch and a fourth switch connected in series,

wherein the capacitor is coupled between a first connection between the first switch and the second switch and a second connection between the third switch and the fourth switch, wherein the first switch is coupled to an output of the current outputting amplifier and the fourth switch is coupled to the gate terminal.

3. The voltage regulator of claim 2 , wherein in a first mode of operation the first and fourth switches are closed and the second and third switches are open, wherein in a second mode of operation the first and fourth switches are open and the second and third switches are closed, and wherein an output of the power FET is coupled to the current outputting amplifier.

4. The voltage regulator of claim 2 , wherein the second switch is coupled to the current source and the third switch is coupled to the voltage source.

5. The voltage regulator of claim 4 , wherein the current source is controlled based on a current output of the current outputting amplifier.

6. The voltage regulator of claim 4 , wherein the voltage source comprises a buck voltage supply.

7. The voltage regulator of claim 1 , wherein a non-inverting input of the current outputting amplifier is coupled to a second voltage source providing a reference voltage, and wherein an inverting input of the current outputting amplifier is coupled to a feedback path coupled to an output of the power FET.

8. The voltage regulator of claim 1 , wherein the capacitor is configured to act as both a flying capacitor and a compensation capacitor.

9. The voltage regulator of claim 1 , wherein the capacitor is not coupled, switchably or not, to a source of the power FET.

10. The voltage regulator of claim 1 , wherein the power FET comprises an re-channel metal-oxide semiconductor (NMOS) transistor.

11. The voltage regulator of claim 1 , wherein the current outputting amplifier comprises a transconductance amplifier.

12. The voltage regulator of claim 1 , wherein the current source is controlled based on a current output of the current outputting amplifier.

13. A method for operating a voltage regulator, comprising:

coupling, in a first mode of operation, a capacitor to a gate terminal of a power field effect transistor (FET);

coupling, in the first mode of operation, the capacitor to an operational transconductor via a current-to-voltage converter and a summer;

decoupling, in the second mode of operation, the capacitor from the operational transconductor;

decoupling, in the second mode of operation, the capacitor from the gate terminal of the power FET;

coupling, in the second mode of operation, the capacitor to a current outputting amplifier via a current source;

coupling, in the second mode of operation, the capacitor to a voltage source separately from the current outputting amplifier, wherein the current outputting amplifier is separate from the voltage source, wherein the operational transconductor is separate from the current outputting amplifier and the voltage source, and wherein an input of the operational transconductor is coupled to an output of the current outputting amplifier; and

decoupling, in the first mode of operation, the capacitor from the voltage source.

14. The method of claim 13 , further comprising using the capacitor as both a flying capacitor and a compensation capacitor.

15. The method of claim 13 , wherein the power FET comprises an n-channel metal-oxide semiconductor (NMOS) transistor.

16. The method of claim 13 , further comprising outputting both proportional and integral terms from a charge pump coupled to the gate terminal of the power FET.

17. The method of claim 13 , further comprising switching between the first mode of operation and the second mode of operation based on a frequency of a clock.

18. The method of claim 17 , wherein a duty cycle of switching between the first mode of operation and the second mode of operation is fixed and based on the frequency of the clock.

19. The method of claim 17 , wherein a duty cycle of switching between the first mode of operation and the second mode of operation is controlled based on a comparison of an output voltage of the voltage regulator to a reference voltage.

20. The method of claim 19 , wherein the duty cycle is based on the frequency of the clock when the output voltage of the voltage regulator is less than the reference voltage.

21. The method of claim 20 , further comprising operating the voltage regulator in the first mode of operation when the output voltage of the voltage regulator is greater than the reference voltage.

22. The method of claim 13 , further comprising:

coupling, in the second mode of operation, the capacitor to the current source; and

decoupling, in the first mode of operation, the capacitor from the current source.

23. The method of claim 22 , further comprising controlling the current source based on a current output of the current outputting amplifier.