IP Library › Granted Patent US 10,333,713
Granted Patent B2
US 10,333,713 · App. 15/290,169 · Granted Jun 25, 2019

Validating internet of things device firmware using a peer-to-peer registry

Inventors: Jeb R. Linton (Manassas, VA); Christopher M. Poulin (Walpole, MA)
Assignee: International Business Machines Corporation
H04L9/3218H04L9/3236H04L63/0876H04L2209/42
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Quick Facts
Patent No.
US 10,333,713
App. No.
15/290,169
Granted
Jun 25, 2019
Kind
B2
Abstract

A computer-implemented method validates Internet of Things (IoT) device firmware levels for peer-to-peer communication in a network using a peer-to-peer registry. Each device in an IoT is registered anonymously by utilizing a unique device identifier and a firmware level in a peer-to-peer registry. Communication rules are provided by the peer-to-peer registry based on the device type and firmware level of each of the devices, in order to validate IoT firmware device levels between the first device and the second device on a network. The first device utilizes a first zero knowledge communication authentication with the second device to get a first assessment and a first proof. The second device utilizes a second zero knowledge communication authentication with the first device to get a second assessment and a second proof. Communication between the first device and the second device via the network is disabled until all assessments are a pass.

Claims (34)

1. A computer-implemented method for validating Internet of Things (loT) firmware device levels for peer-to-peer communication via a network using a peer-to-peer registry, the computer-implemented method comprising:

registering each device in an loT anonymously by utilizing a unique device identifier and a firmware level in a peer-to-peer registry, wherein said peer-to-peer registry utilizes a cryptographically verifiable trusted computing algorithm for devices communicating on a network through which devices in the loT communicate;

providing communication rules by the peer-to-peer registry based on device type and firmware level of each of the devices;

utilizing the communication rules between a first device and a second device to establish a session to validate loT device firmware levels between the first device and the second device, wherein the first device utilizes a first zero knowledge communication authentication with the second device to get a first assessment and a first proof, wherein the second device utilizes a second zero knowledge communication authentication with the first device to get a second assessment and a second proof, wherein the first zero knowledge communication authentication and the second zero knowledge communication authentication are based on a Succinct Computational Integrity and Privacy (SCIP) protocol, wherein the first and second assessments are outputs of respective loT firmware in the second device and the first device using a known input, wherein the first proof and the second proof are derived from reports of hashed values of respective intermediate states during execution of loT firmware in the second device and the first device, wherein the hashed values of the respective intermediate states during execution of the loT firmware in the first device are made up of a string of bits;

determining, by one or more processors, that a predetermined portion of the string of bits matches a known string of correct bits for the first proof, wherein the predetermined portion is less than all of the string of bits;

in response to determining that the predetermined portion of the string of bits matches the known string of correct bits for the first proof, determining that firmware in the first device is compatible with firmware in the second device;

checking the second proof by the first device to get a third assessment;

checking the first proof by the second device to get a fourth assessment; and

disabling communication between the first device and the second device via the network until the first assessment is a pass and the second assessment is a pass and the third assessment is a pass and the fourth assessment is a pass.

2. The computer-implemented method of claim 1 , wherein the respective intermediate states of the first device and the second device are contents from a program counter, a stack pointer, and OS flags in processors running on the first device and the second device.

3. The computer-implemented method of claim 1 , wherein the respective intermediate states of the first device and the second device are a hard state and a soft state of the cores in the first device and the second device, and wherein the hard state and the soft state of the cores are contents of an L1 instruction cache, an L1 data cache, an L2 cache, a condition register register (CRR), a link count register (LCR), a general purpose register (GPR), and a floating point register (FPR) within each of the cores.

4. A computer program product comprising one or more computer readable storage mediums, and program instructions stored on at least one of the one or more computer readable storage mediums, the stored program instructions comprising:

program instructions to register each device in an Internet of Things (loT) anonymously by utilizing a unique device identifier and a firmware level in a peer-to-peer registry, wherein said peer-to-peer registry utilizes a cryptographically verifiable trusted computing algorithm for devices communicating on a network through which devices in the loT communicate;

program instructions to provide communication rules by the peer-to-peer registry based on device type and firmware level of each of the devices;

program instructions to utilize the communication rules between a first device and a second device to establish a session to validate loT device firmware levels between the first device and the second device, wherein the first device utilizes a first zero knowledge communication authentication with the second device to get a first assessment and a first proof, wherein the second device utilizes a second zero knowledge communication authentication with the first device to get a second assessment and a second proof, wherein the first zero knowledge communication authentication and the second zero knowledge communication authentication are based on Zero Knowledge Succinct Non-Interactive Arguments of Knowledge (zk-SNARKs), wherein the first and second assessments are outputs of respective loT firmware in the second device and the first device using a known input, and wherein the first proof and the second proof are derived from reports of hashed values of respective intermediate states during execution of loT firmware in the second device and the first device, wherein the hashed values of the respective intermediate states during execution of the loT firmware in the first device are made up of a string of bits;

program instructions to determine that a predetermined portion of the string of bits matches a known string of correct bits for the first proof, wherein the predetermined portion is less than all of the string of bits;

program instructions to, in response to determining that the predetermined portion of the string of bits matches the known string of correct bits for the first proof, determine that firmware in the first device is compatible with firmware in the second device;

program instructions to check the second proof by the first device to get a third assessment;

program instructions to check the first proof by the second device to get a fourth assessment; and

program instructions to disable communication between the first device and the second device via the network until the first assessment is a pass and the second assessment is a pass and the third assessment is a pass and the fourth assessment is a pass.

5. The computer program product of claim 4 , wherein the respective intermediate states of the first device and the second device are contents from a program counter, a stack pointer, and OS flags in processors running on the first device and the second device.

6. The computer program product of claim 4 , wherein the respective intermediate states of the first device and the second device are a hard state and a soft state of the cores in the first device and the second device, and wherein the hard state and the soft state of the cores are contents of an L1 instruction cache, an L1 data cache, an L2 cache, a condition register register (CRR), a link count register (LCR), a general purpose register (GPR), and a floating point register (FPR) within each of the cores.

7. The computer program product of claim 4 , wherein the stored program instructions are provided as a service in a cloud environment.

8. A computer system comprising one or more processors, one or more computer readable memories, and one or more computer readable storage mediums, and program instructions stored on at least one of the one or more computer readable storage mediums for execution by at least one of the one or more processors via at least one of the one or more computer readable memories, the stored program instructions comprising:

program instructions to register each device in an Internet of Things (loT) anonymously by utilizing a unique device identifier and a firmware level in a peer-to-peer registry, wherein said peer-to-peer registry utilizes a cryptographically verifiable trusted computing algorithm for devices communicating on a network through which devices in the loT communicate;

program instructions to provide communication rules by the peer-to-peer registry based on device type and firmware level of each of the devices;

program instructions to utilize the communication rules between a first device and a second device to establish a session to validate loT device firmware levels between the first device and the second device, wherein the first device utilizes a first zero knowledge communication authentication with the second device to get a first assessment and a first proof, wherein the second device utilizes a second zero knowledge communication authentication with the first device to get a second assessment and a second proof, wherein the first zero knowledge communication authentication and the second zero knowledge communication authentication are based on Probabilistically Checkable Proofs (PCPs), wherein the first and second assessments are outputs of respective loT firmware in the second device and the first device using a known input, and wherein the first proof and the second proof are derived from reports of hashed values of respective intermediate states during execution of loT firmware in the second device and the first device, wherein the hashed values of the respective intermediate states during execution of the loT firmware in the first device are made up of a string of bits;

program instructions to determine that a predetermined portion of the string of bits matches a known string of correct bits for the first proof, wherein the predetermined portion is less than all of the string of bits;

program instructions to, in response to determining that the predetermined portion of the string of bits matches the known string of correct bits for the first proof, determine that firmware in the first device is compatible with firmware in the second device;

program instructions to check the second proof by the first device to get a third assessment;

program instructions to check the first proof by the second device to get a fourth assessment; and

program instructions to disable communication between the first device and the second device via the network until the first assessment is a pass and the second assessment is a pass and the third assessment is a pass and the fourth assessment is a pass.

9. The computer system of claim 8 , wherein the respective intermediate states of the first device and the second device are contents from a program counter, a stack pointer, and OS flags in processors running on the first device and the second device.

10. The computer system of claim 8 , wherein the respective intermediate states of the first device and the second device are a hard state and a soft state of the cores in the first device and the second device, and wherein the hard state and the soft state of the cores are contents of an L1 instruction cache, an L1 data cache, an L2 cache, a condition register register (CRR), a link count register (LCR), a general purpose register (GPR), and a floating point register (FPR) within each of the cores.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2016
From: LINTON, JEB R.; POULIN, CHRISTOPHER M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039983/0711 →
Continuity (1)
Related Publication 20180102901A1 · Apr 12, 2018