IP Library › Granted Patent US 10,338,031
Granted Patent B2
US 10,338,031 · App. 15/446,092 · Granted Jul 2, 2019

Component-embedded substrate and substrate flaw detecting method

Inventors: Shigeru Tago (Nagaokakyo, JP); Hirofumi Shinagawa (Nagaokakyo, JP); Toshiro Adachi (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
G01N29/043G01N29/11H01L23/00H01L23/5383H01L23/5384H01L23/552H01L24/16H01L25/0657H05K1/0218H05K1/0269G01N2291/015G01N2291/048G01N2291/2697H01L23/5386H01L23/5389H01L2224/04105H01L2224/16227H01L2225/06517H01L2225/06548H01L2225/06555H01L2924/14H01L2924/3025H01L2924/3512H05K1/185H05K2203/0285
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Quick Facts
Patent No.
US 10,338,031
App. No.
15/446,092
Granted
Jul 2, 2019
Kind
B2
Abstract

A component-embedded substrate includes a multilayer body including a plurality of insulating layers stacked in a stacking direction, an embedded component embedded in the multilayer body, and planar conductors disposed on both sides of the embedded component in the stacking direction, the planar conductors overlapping the embedded component. The planar conductors each include a plurality of openings that overlap the embedded component over substantially the entire region occupied by the embedded component, as seen in the stacking direction.

Claims (32)

1. A component-embedded substrate comprising:

a multilayer body including a plurality of insulating layers stacked in a stacking direction;

an embedded component embedded in the multilayer body;

a planar conductor disposed on one side of the embedded component in the stacking direction, the planar conductor overlapping the embedded component; and

one or more wiring conductors disposed on the one side of the embedded component in the stacking direction, the one or more wiring conductors being different from the planar conductor and connecting to the embedded component or the planar conductor in the insulating layers; wherein

the planar conductor includes a plurality of openings overlapping the embedded component over an entire region occupied by the embedded component, as seen in the stacking direction;

the one or more wiring conductors are arranged to overlap the planar conductor and the embedded component; and

at least one of the plurality of openings do not overlap at least a portion of any of the one or more wiring conductors different from the planar conductor, as seen in the stacking direction.

2. The component-embedded substrate according to claim 1 , wherein the one or more wiring conductors include a line conductor extending around the openings and overlapping the embedded component and the planar conductor, as seen in the stacking direction.

3. The component-embedded substrate according to claim 1 , wherein the planar conductor is connected to a ground potential.

4. The component-embedded substrate according to claim 3 , wherein the embedded component includes an active element.

5. The component-embedded substrate according to claim 1 , wherein the plurality of openings in the planar conductor are arranged at regular intervals.

6. The component-embedded substrate according to claim 5 , wherein the planar conductor has a mesh shape or a lattice shape, as seen through the multilayer body in the stacking direction.

7. The component-embedded substrate according to claim 1 , wherein

a plurality of planar conductors are provided; and

the plurality of planar conductors are disposed on both the one side and the other side of the embedded component in the stacking direction.

8. The component-embedded substrate according to claim 7 , wherein the plurality of planar conductors sandwich the embedded component to define a shield electrode.

9. The component-embedded substrate according to claim 1 , further comprising a shield electrode including the planar conductor, disposed inside the multilayer body and connected to a ground potential.

10. The component-embedded substrate according to claim 1 , further comprising an oscillation circuit embedded in the embedded component at a location spaced from a position where the embedded component and a surface mount device overlap.

11. The component-embedded substrate according to claim 10 , wherein the planar conductor overlaps an entirety of the oscillation circuit.

12. The component-embedded substrate according to claim 1 , wherein the planar conductor overlaps an entire region occupied by the embedded component except for a region where the embedded component and a surface mount device overlap, as seen in the stacking direction.

13. The component-embedded substrate according to claim 1 , further comprising interlayer connection conductors in the multilayer body to connect the one or more wiring conductors.

14. The component-embedded substrate according to claim 1 , wherein the embedded component includes an oscillation circuit and is electromagnetically shielded from two sides.

15. A substrate flaw detecting method comprising:

transmitting ultrasonic waves from one side of the component-embedded substrate according to claim 1 in the stacking direction;

receiving the ultrasonic waves transmitted through the component-embedded substrate; and

obtaining information of an internal structure of the component-embedded substrate based on an intensity of the ultrasonic waves received.

16. The method of claim 15 , wherein the obtaining information includes analyzing a detection signal of ultrasonic vibration to generate a flow detection signal.

17. The method of claim 15 , wherein the obtaining information includes obtaining information including image data representing the internal structure of the component-embedded substrate.

18. The method of claim 15 , wherein the obtaining information includes obtaining information regarding presence or absence of cracks in the internal structure of the component-embedded substrate.

19. The method of claim 15 , wherein the method is performed using a substrate flaw detecting apparatus including a transmitting circuit, a transmitting ultrasonic transducer, a receiving ultrasonic transducer, a receiving circuit, and an analyzer.

20. The method of claim 15 , wherein the method is performed using a substrate flaw detecting apparatus including an ultrasonic transducer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2017
From: TAGO, SHIGERU; SHINAGAWA, HIROFUMI; ADACHI, TOSHIRO
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 041417/0856 →
Priority Claims (1)
JP 2014-178685 · Sep 3, 2014 · national
Continuity (2)
Continuation PCTJP2015073952 · Aug 26, 2015
Related Publication 20170176392A1 · Jun 22, 2017