Method of scheduling system-on-chip including real-time shared interface

1. A scheduling method performed by a scheduler located between a plurality of masters and a slave, the scheduling method comprising:

receiving a plurality of access requests from the plurality of masters;

setting the plurality of access requests in a plurality of registers;

scheduling the plurality of access requests, wherein the scheduling of the plurality of access requests comprises:

setting a plurality of time limit values based on the plurality of access requests, and

determining whether a system satisfies preconditions for operations, based on the plurality of time limit values; and

transmitting, when the system does not satisfy the preconditions for operations, a schedule uncontrollability message to the plurality of masters.

2. The scheduling method of claim 1 , wherein the scheduling of the plurality of access requests further comprises:

when the system satisfies the preconditions for operations, selecting an access request corresponding to a minimum time limit value which is greater than ‘0’ among the plurality of time limit values;

transmitting setting data included in the selected access request to an interface; and

changing the plurality of time limit values, wherein

the interface is shared by the plurality of masters.

3. The scheduling method of claim 2 , wherein the setting of the plurality of time limit values comprises:

calculating result values by dividing a plurality of critical time boundaries of the plurality of access requests by a unit operation time; and

setting integers which are not less than the result values to be the plurality of time limit values.

4. The scheduling method of claim 2 , wherein the determining of whether the system satisfies the preconditions for operations comprises:

converting time limit values which are greater than ‘0’ among the plurality of time limit values into reciprocal numbers and adding the reciprocal numbers; and

determining whether a result of adding the reciprocal numbers is equal to or less than ‘1’.

5. The scheduling method of claim 2 , wherein the selecting of the access request comprises:

comparing the plurality of time limit values with each other;

when two or more of the access requests correspond to the minimum time limit value which is greater than ‘0’, setting priority values of the respective two or more access requests; and

selecting an access request corresponding to a minimum priority value among the two or more access requests corresponding to the minimum time limit value which is greater than ‘0’.

6. The scheduling method of claim 5 , wherein, when only one of the access requests corresponds to the minimum time limit value which is greater than ‘0’, the selecting of the access request further comprises selecting the access request corresponding to the minimum time limit value which is greater than ‘0’.

7. The scheduling method of claim 2 , wherein the changing of the plurality of time limit values comprises:

changing the time limit value of the selected access request to ‘0’; and

decreasing the time limit values of the non-selected access requests among the plurality of access requests by ‘1’.

8. The scheduling method of claim 2 , wherein:

the interface corresponds to at least one protocol among an inter-integrated circuit interface (I2C interface), a universal asynchronous receiver/transmitter (UART), a serial peripheral interface (SPI), and a high-speed inter-chip (HSIC), and

a number of the plurality of registers corresponds to a number of the plurality of masters.

9. The scheduling method of claim 2 , wherein:

the scheduling of the plurality of access requests further comprises determining whether all of the plurality of time limit values are ‘0’,

wherein the determining whether the system satisfies the preconditions for operations is performed, when all of the plurality of time limit values are greater than ‘0’.

10. The scheduling method of claim 2 , wherein the selecting of the access request comprises:

comparing the plurality of time limit values with each other; and

when two or more of the access requests correspond to the minimum time limit value which is greater than ‘0’, selecting one of the two or more access requests corresponding to the minimum time limit value which is greater than ‘0’.

11. A method of scheduling a system-on-chip (SoC) which includes a plurality of masters, an interface, a slave, and a scheduler, the method comprising:

transmitting, by the plurality of masters, a plurality of access requests, which are to be transmitted to the slave, to the scheduler;

receiving, by the scheduler, the plurality of access requests from the plurality of masters;

setting, by the scheduler, the plurality of access requests in a plurality of registers;

scheduling, by the scheduler, the plurality of access requests; and

receiving, by one of the plurality of masters, an interrupt transmitted from the slave, wherein:

the scheduler comprises a first register, a second register, a first down-counter, a second down-counter, a comparator, and a controller,

the scheduling of the plurality of access requests comprises:

setting, with the controller, a plurality of time limit values based on the plurality of access requests and respectively storing the plurality of time limit values in the first down-counter and the second down-counter;

determining, with the controller, whether a system satisfies preconditions for operations, based on the plurality of time limit values;

selecting with the controller, when the system satisfies the preconditions for operations, an access request corresponding to a minimum time limit value which is greater than ‘0’ among the plurality of time limit values;

transmitting, by the controller, setting data included in the selected access request to the interface;

receiving an interrupt from the slave via the interface in response to the interface transmitting the setting data to the slave;

transmitting, by the controller, the interrupt received from the interface to a master corresponding to the selected access request;

changing, by the controller, the plurality of time limit values; and

determining, by the controller, whether all of the plurality of time limit values are ‘0’, and

when all of the plurality of time limit values are not ‘0’, the controller determines repeatedly whether the system satisfies the preconditions for operations.

12. The method of claim 11 , wherein the selecting of the access request comprises:

transmitting, by the controller, a comparison signal to the first down-counter and the second down-counter;

transmitting, by the first down-counter and the second down-counter, the plurality of time limit values stored therein to the comparator;

comparing, with the comparator, the plurality of time limit values with each other and transmitting a minimum time limit value which is greater than ‘0’ to the controller; and

selecting, with the controller, the access request corresponding to the minimum time limit value which is greater than ‘0’.

13. The method of claim 11 , wherein the changing of the plurality of time limit values comprises:

transmitting, by the controller, a reset signal to the first down-counter, which stores the time limit value of the selected access request, and a counting pulse to the second down-counter that does not store the time limit value of the selected access request;

changing, by the first down-counter that receives the reset signal, the time limit value stored therein to ‘0’; and

decreasing, by the second down-counter that receives the counting pulse, the time limit value stored therein by ‘1’.

14. A method executed by a scheduling circuit, the method comprising:

storing, in each of a plurality of registers of the scheduling circuit, a request to access a slave processor that is received from a master processor, among a plurality of master processors, corresponding to the register;

determining with a control circuit, for each of the access requests, a time limit for delaying execution of the access request based on information provided by the access request;

determining, with a comparator circuit, an access request among the access requests having a minimum of the time limits; and

transmitting the access request having the minimum time limit to the slave processor.

15. The method of claim 14 , further comprising determining, with the control circuit, whether the access requests can begin execution by slave processors within their respective time limits.

16. The method of claim 14 , further comprising:

receiving, from the slave processor, an indication that execution of a current access request has completed;

re-determining, with the comparator circuit, an access request among remaining access requests having a minimum of the time limits; and

transmitting, by the control circuit, the access request having the re-determined minimum time limit to the slave processor.

17. The method of claim 16 , further comprising reducing, with a counter circuit, the time limit of each of the remaining access requests in accordance with the time expired during the slave processor's execution of the current access request.

18. The method of claim 14 , wherein the access requests received from master processors are concurrently stored in the registers.