IP Library Granted Patent US 10,340,255
Granted Patent B2
US 10,340,255 · App. 16/036,413 · Granted Jul 2, 2019

Semiconductor apparatus and semiconductor system including the same

Inventor: Kwan Dong Kim (Cheongju-si, KR)
Assignee: SK hynix Inc.
H01L25/0657H01L23/522H01L24/09H01L24/17H01L27/10897H01L27/1116H01L27/11286H01L24/06H01L24/48H01L24/49H01L2224/16146H01L2224/16235H01L2224/48145H01L2224/48227
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Quick Facts
Patent No.
US 10,340,255
App. No.
16/036,413
Granted
Jul 2, 2019
Kind
B2
Abstract

A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips may be configured based on a load value of the semiconductor apparatus.

Claims (66)

1. A semiconductor apparatus comprising:

a package substrate; and

a semiconductor chip,

wherein the package substrate comprises a substrate pad coupled with a package ball,

wherein the semiconductor chip comprises:

a main pad coupled with the substrate pad;

a first buffer coupled with the main pad; and

an auxiliary pad coupled with the first buffer.

2. The semiconductor apparatus according to claim 1 ,

wherein transmission of a signal from the semiconductor chip to an external of the semiconductor chip is performed through the substrate pad, and

wherein reception of a signal received externally from the semiconductor chip is performed through the substrate pad.

3. The semiconductor apparatus according to claim 1 , wherein the main pad is wire-bonded with the substrate pad, and the main pad and the auxiliary pad are indirectly coupled with each other.

4. The semiconductor apparatus according to claim 1 , wherein the main pad is coupled with the substrate pad through a through electrode, and the main pad and the auxiliary pad are not coupled directly with each other.

5. The semiconductor apparatus according to claim 1 , further comprising:

a second buffer coupled with the first buffer, the auxiliary pad and an internal circuit of the semiconductor chip.

6. The semiconductor apparatus according to claim 5 , wherein the second buffer buffers a signal outputted from the first buffer and provides the buffered signal to the internal circuit of the semiconductor chip, or buffers a signal outputted from the internal circuit and provides the buffered signal to the first buffer.

7. A semiconductor apparatus comprising:

a package substrate; and

a first semiconductor chip and a second semiconductor chip stacked with the package substrate,

wherein the package substrate comprises a substrate pad coupled with a package ball,

wherein the first semiconductor chip comprises:

a first main pad coupled with the substrate pad;

a first buffer coupled with the first main pad;

a first auxiliary pad coupled with the first buffer; and

a second buffer coupled with the first buffer and the first auxiliary pad, and

wherein the second semiconductor chip comprises:

a second auxiliary pad coupled with the first auxiliary pad.

8. The semiconductor apparatus according to claim 7 ,

wherein transmission of a signal from the semiconductor chip to an external of the semiconductor chip is performed through the substrate pad, and

wherein reception of a signal received externally from the semiconductor chip is performed through the substrate pad.

9. The semiconductor apparatus according to claim 7 , wherein the first main pad is wire-bonded with the substrate pad, and the first main pad is indirectly coupled with the first auxiliary pad.

10. The semiconductor apparatus according to claim 7 , wherein the second buffer buffers a signal outputted from the first buffer and provides the buffered signal to an internal circuit of the first semiconductor chip, or buffer a signal outputted from the internal circuit and provides the buffered signal to the first buffer.

11. The semiconductor apparatus according to claim 7 , wherein the second auxiliary pad is wire-bonded with the first auxiliary pad.

12. The semiconductor apparatus according to claim 11 , further comprising:

a third semiconductor chip stacked with the first and second semiconductor chips over the package substrate,

wherein the third semiconductor chips comprises a third auxiliary pad, and

wherein the third auxiliary pad of the third semiconductor chip is wire-bonded with the second auxiliary pad.

13. The semiconductor apparatus according to claim 12 ,

wherein the second semiconductor chip further comprises a second main pad, and the third semiconductor chip further comprises a third main pad, and

wherein the second main pad and the third main pad are not wire-bonded with the substrate pad.

14. The semiconductor apparatus according to claim 7 ,

wherein the second semiconductor chip further comprises:

a second main pad;

a third buffer coupled with the second main pad; and

a fourth buffer coupled with the third buffer and the second auxiliary pad, and

wherein the second main pad is not wire-bonded with the substrate pad.

15. A semiconductor apparatus comprising:

a package substrate; and

a first semiconductor chip stacked over the package substrate,

wherein the package substrate comprises:

a substrate pad which is coupled with a package ball, and

wherein the first semiconductor chip comprises:

a main pad coupled with the substrate pad;

an auxiliary pad; and

a buffer configured to couple the main pad and the auxiliary pad.

16. The semiconductor apparatus according to claim 15 ,

wherein the semiconductor apparatus further comprises a plurality of semiconductor chips which are stacked with the first semiconductor chip,

wherein each of the plurality of semiconductor chips comprises a main pad and an auxiliary pad, and

wherein the auxiliary pads of adjacent semiconductor chips among the plurality of semiconductor chips are wire-bonded with each other, and main pads of the plurality of semiconductor chips are not wire-bonded with the first substrate pad.

17. The semiconductor apparatus according to claim 15 ,

wherein the semiconductor apparatus further comprises a plurality of semiconductor chips which are stacked with the first semiconductor chip,

wherein each of the plurality of semiconductor chips comprises a main pad and an auxiliary pad,

wherein the first semiconductor chip and the plurality of semiconductor chips are classified into first to n^th groups, the main pad of at least one semiconductor chip of each group is wire-bonded with the substrate pad, and the auxiliary pads of semiconductor chips of each group are wire-bonded with each other, and

wherein n is an integer equal to or greater than two.

18. The semiconductor apparatus according to claim 16 ,

wherein the auxiliary pads of adjacent semiconductor chips among the plurality of semiconductor chips in the each group are wire-bonded with each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2018
From: KIM, KWAN DONG
To: SK HYNIX INC.
Reel/Frame 046361/0368 →
Priority Claims (1)
KR 10-2016-0113798 · Sep 5, 2016 · national
Continuity (2)
Continuation In Part 15483444 · Apr 10, 2017
Related Publication 20180323176A1 · Nov 8, 2018
Cited By (1)
US 12,288,596