Integrated circuit having FinFETS with different fin profiles

1. A method of forming an integrated circuit, comprising:

forming a first top fin, a second top fin, and a third top fin extending from a substrate;

forming a first mask over the first top fin;

forming a second mask over the second top fin and the third top fin;

removing a portion of the substrate to form a first base fin and a second base fin, the first top fin extending from the first base fin, the second top fin and the third top fin extending from the second base fin; and

after removing the portion of the substrate to form the first base fin and the second base fin, reducing a width of the first base fin.

2. The method of claim 1 , wherein a first angle of a sidewall of the first base fin relative to a top surface of the first top fin is different than a second angle of a sidewall of the first top fin relative to the top surface of the first top fin.

3. The method of claim 1 , further comprising, prior to reducing the width of the first base fin, removing the first mask.

4. The method of claim 1 , further comprising, prior to reducing the width of the first base fin:

removing the first mask and the second mask; and

forming a third mask over the second top fin and the third top fin.

5. The method of claim 1 , further comprising forming a dielectric material, the dielectric material extending at least partially along sidewalls of the first top fin, the second top fin, and the third top fin.

6. The method of claim 5 , wherein the dielectric material extends between the second top fin and the third top fin.

7. A method of forming an integrated circuit, comprising:

forming a first FinFET over a substrate, the first FinFET having a first fin with a non-tiered fin profile; and

forming a second FinFET over the substrate, the second FinFET having a second fin and a third fin each extending from a same lower tier, wherein the same lower tier forms a step along opposing sides of each of the second fin and the third fin, wherein a longitudinal axis of the second fin and a longitudinal axis of the third fin are substantially parallel along a first direction, the second fin extending along the first direction further than the third fin;

wherein the forming the first FinFET and the forming the second FinFET comprises, after forming the first fin, the second fin, and the third fin, forming an isolation material adjacent the first fin, the second fin, and the third fin, the isolation material extending along sidewalls of the same lower tier and an upper surface of the same lower tier between the second fin and the third fin.

8. The method of claim 7 , wherein the upper surface of the same lower tier extends away from opposing sides of the second fin and the third fin.

9. The method of claim 7 , wherein an upper portion of the first fin, the second fin, and the third fin are formed simultaneously.

10. The method of claim 7 , wherein forming the first FinFET and the second FinFET comprises:

forming first patterned mask layer over the substrate, the first patterned mask layer having a first portion, a second portion, and a third portion over the substrate;

etching the substrate to form an upper portion of the first fin, the second fin, and the third fin;

forming a second patterned mask layer over the substrate, the second patterned mask layer having a first portion and a second portion, the first portion of the second patterned mask layer formed over the first portion of the first patterned mask layer, the second portion of the second patterned mask layer formed over the second portion and the third portion of the first patterned mask layer;

etching the substrate to form the same lower tier and a lower portion of the first fin;

removing the second patterned mask layer;

forming a third patterned mask layer, the third patterned mask layer protecting the second fin and the third fin; and

thinning the lower portion of the first fin.

11. The method of claim 7 , wherein the first FinFET is a pull-up transistor of an SRAM device and the second FinFET comprises a pull-down transistor of the SRAM device.

12. The method of claim 11 , further comprising forming a third FinFET, wherein the third FinFET comprises a pass gate transistor formed over the second fin and the third fin.

13. The method of claim 12 , where a gate structure of the pass gate transistor overlaps an end of the second fin.

14. A method of forming an integrated circuit, comprising:

forming a first top fin, a second top fin, and a third top fin, the first top fin extending from a first base fin, the second top fin and the third top fin extending from a second base fin;

forming a first mask over the second top fin and the third top fin;

thinning a width of the first base fin while the second top fin and the third top fin are protected by the first mask, wherein sidewalls of the first top fin are unmasked during the thinning, the first top fin remaining after the thinning; and

removing the first mask.

15. The method of claim 14 , wherein thinning the width of the first base fin forms a non-tiered fin.

16. The method of claim 14 , further comprising:

forming a second mask over a substrate, the second mask defining a pattern for the first top fin, the second top fin, and the third top fin;

etching the substrate using the second mask as a mask;

forming a third mask over the substrate, the third mask defining a pattern for the first base fin and the second base fin; and

etching the substrate using the third mask as a mask.

17. The method of claim 14 , wherein an angle of a sidewall of the first base fin relative to a first line parallel to an upper surface of the second base fin is different than an angle of the first top fin relative to the first line.

18. The method of claim 14 , further comprising forming an isolation material between the first base fin and the second base fin.

19. The method of claim 18 , wherein the isolation material extends above an upper surface of the first base fin and the second base fin.

20. The method of claim 18 , wherein the isolation material is interposed between the second top fin and the third top fin.