Asymmetric gated fin field effect transistor (FET) (finFET) diodes
Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.
1. An asymmetric gated fin Field Effect Transistor (FET) (finFET) diode, comprising:
a substrate comprising:
a first-type well region; and
a fin disposed in a direction, the fin comprising:
a first source/drain region having a first length in the direction, wherein, within the first length, the first source/drain region comprises a first-type doped material disposed in the fin and extending in the direction from a first side to a second side of the first-type doped material;
a second source/drain region having a second length in the direction that is larger than the first length, wherein, within the second length, the second source/drain region comprises a second-type doped material disposed in the fin and extending in the direction from a first side to a second side of the second-type doped material; and
a gate region disposed between the first source/drain region and the second source/drain region having a third length in the direction that is equal to the second length plus a difference of the second length and the first length.
2. The asymmetric gated finFET diode of claim 1 , wherein:
the first source/drain region further comprises:
a first spacer disposed over the fin and on the first side of the first-type doped material; and
a second spacer disposed over the fin and on the second side of the first-type doped material;
the second source/drain region further comprises:
a first spacer disposed over the fin and on the first side of the second-type doped material; and
a second spacer disposed over the fin and on the second side of the second-type doped material; and
the gate region further comprises a gate disposed over the fin.
3. The asymmetric gated finFET diode of claim 1 , wherein the gate region comprises:
a first spacer disposed over the fin and adjacent to the first source/drain region; and
a second spacer disposed over the fin and adjacent to the second source/drain region.
4. The asymmetric gated finFET diode of claim 1 , wherein:
the first-type well region comprises an N-type well region;
the first-type doped material of the first source/drain region comprises an N-type doped material; and
the second-type doped material of the second source/drain region comprises a P-type doped material.
5. The asymmetric gated finFET diode of claim 1 , wherein:
the second source/drain region comprises an anode; and
the first source/drain region comprises a cathode.
6. The asymmetric gated finFET diode of claim 1 , wherein:
the first-type well region comprises a P-type well region;
the first-type doped material of the first source/drain region comprises a P-type doped material; and
the second-type doped material of the second source/drain region comprises an N-type doped material.
7. The asymmetric gated finFET diode of claim 6 , wherein:
the second source/drain region comprises a cathode; and
the first source/drain region comprises an anode.
8. The asymmetric gated finFET diode of claim 1 , wherein the first length is approximately equal to a ground rule minimum length.
9. The asymmetric gated finFET diode of claim 1 , further comprising a bulk doped plug disposed in the first-type well region and under the first source/drain region, wherein the bulk doped plug comprises the first-type doped material.
10. The asymmetric gated finFET diode of claim 1 , further comprising:
a plurality of first source/drain regions, wherein each first source/drain region has the first length in the direction and comprises the first-type doped material disposed in the fin;
a plurality of second source/drain regions, wherein each second source/drain region has the second length in the direction and comprises the second-type doped material disposed in the fin; and
a plurality of gate regions, wherein each gate region is formed between a corresponding second source/drain region and a corresponding first source/drain region and has the third length in the direction.
11. An asymmetric gated fin Field Effect Transistor (FET) (finFET) diode, comprising:
a means for providing a substrate comprising:
a first-type well region; and
a fin disposed in a direction;
a means for providing a first source/drain region having a first length in the direction, wherein, within the first length, the first source/drain region comprises a first-type doped material disposed in the fin and extending in the direction from a first side to a second side of the first-type doped material;
a means for providing a second source/drain region having a second length in the direction that is larger than the first length, wherein, within the second length, the second source/drain region comprises a second-type doped material disposed in the fin and extending in the direction from a first side to a second side of the second-type doped material; and
a means for providing a gate region disposed between the first source/drain region and the second source/drain region having a third length in the direction that is equal to the second length plus a difference of the second length and the first length.
12. A method of manufacturing an asymmetric gated fin Field Effect Transistor (FET) (finFET) diode, comprising:
providing a substrate comprising a first-type well region and a fin disposed in a direction;
forming a gate region corresponding to the fin, wherein the gate region has a third length in the direction;
disposing a first-type doped material in a first source/drain region in the fin, wherein the first source/drain region has a first length in the direction smaller than the third length, the first source/drain region extending in the direction from a first side to a second side of the first-type doped material; and
disposing a second-type doped material in a second source/drain region in the fin, wherein the second source/drain region has a second length in the direction larger than the first length and smaller than the third length, the second source/drain region extending in the direction from a first side to a second side of the second-type doped material, wherein the gate region is disposed between the first source/drain region and the second source/drain region and wherein the third length is equal to the second length plus a difference of the second length and the first length.
13. The method of claim 12 , wherein:
providing the substrate comprises providing the substrate comprising an N-type well region and the fin;
disposing the first-type doped material comprises disposing an N-type doped material in the first source/drain region in the fin; and
disposing the second-type doped material comprises disposing a P-type doped material in the second source/drain region in the fin.
14. The method of claim 12 , wherein:
providing the substrate comprises providing the substrate comprising a P-type well region and the fin;
disposing the first-type doped material comprises disposing a P-type doped material in the first source/drain region in the fin; and
disposing the second-type doped material comprises disposing an N-type doped material in the second source/drain region in the fin.
15. An apparatus, comprising:
an electrostatic discharge (ESD) protection circuit, comprising:
a positive surge asymmetric gated fin Field Effect Transistor (FET) (finFET) diode coupled to a signal pin and a voltage rail, comprising:
a substrate comprising:
an N-type well region; and
a fin disposed in a direction;
a first source/drain region having a first length in the direction, wherein the first source/drain region of the positive surge asymmetric gated finFET diode comprises an N-type doped material disposed in the fin and extending in the direction from a first side to a second side of the N-type doped material;
a second source/drain region having a second length in the direction that is larger than the first length, wherein the second source/drain region of the positive surge asymmetric gated finFET diode comprises a P-type doped material disposed in the fin and extending in the direction from a first side to a second side of the P-type doped material; and
a gate region disposed between the second source/drain region and the first source/drain region of the positive surge asymmetric gated finFET diode and having a third length in the direction that is equal to the second length plus a difference of the second length and the first length; and
a negative surge asymmetric gated finFET diode coupled to the signal pin and a ground rail, comprising:
the substrate comprising:
a P-type well region; and
a fin disposed in the direction;
a first source/drain region having the first length in the direction, wherein the first source/drain region of the negative surge asymmetric gated finFET diode comprises a P-type doped material disposed in the fin;
a second source/drain region having the second length in the direction, wherein the second source/drain region of the negative surge asymmetric gated finFET diode comprises an N-type doped material disposed in the fin; and
a gate region disposed between the second source/drain region and the first source/drain region of the negative surge asymmetric gated finFET diode and having the third length in the direction.
16. The apparatus of claim 15 , wherein the third length is approximately equal to the second length plus a difference of the second length and the first length.
17. The apparatus of claim 15 , wherein:
the second source/drain region of the positive surge asymmetric gated finFET diode comprises an anode;
the first source/drain region of the positive surge asymmetric gated finFET diode comprises a cathode;
the second source/drain region of the negative surge asymmetric gated finFET diode comprises a cathode; and
the first source/drain region of the negative surge asymmetric gated finFET diode comprises an anode.
18. The apparatus of claim 15 , wherein the first length is approximately equal to a ground rule minimum length.
19. The apparatus of claim 15 , wherein:
the positive surge asymmetric gated finFET diode further comprises a bulk doped plug disposed in the N-type well region and under the first source/drain region of the positive surge asymmetric gated finFET diode, wherein the bulk doped plug comprises the N-type doped material; and
the negative surge asymmetric gated finFET diode comprises a bulk doped plug disposed in the P-type well region and under the first source/drain region of the negative surge asymmetric gated finFET diode, wherein the bulk doped plug comprises the P-type doped material.