Soft decision LDPC decoder with improved LLR from neighboring bits

1. A method of providing a log likelihood ratio (LLR) of at least one bit representing a charge state of a target cell of a plurality of cells of a non-volatile memory to a low-density parity check (LDPC) decoder, each of the plurality of cells capable of being in any one of a plurality of cell charge states, the method comprising:

storing in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory;

determining a cell charge state of the target cell and a cell charge state of at least one of a plurality of neighboring cells;

calculating a value representative of the difference in at least one of a plurality of charge states of the target cell and the at least one of the plurality of neighboring cells;

comparing the calculated value with at least one predetermined threshold value representative of the degree of disturbance effect the charge state of the at least one of the plurality of neighboring cells has on the charge state of the target cell;

setting at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value;

extracting a new LLR value from the look-up table using the at least one address bit; and

providing the new LLR value of the at least one bit representing the charge state of the target cell to the LDPC decoder.

2. The method of claim 1 , wherein determining the cell charge state of the target cell or neighboring cell comprises performing multiple reads on each target cell or neighboring cell at varying threshold voltages.

3. The method of claim 1 , further comprising assigning a numerical value to each of the plurality of cell charge states.

4. The method of claim 3 , wherein the plurality of cell charge states and their associated numerical values are stored in the non-volatile memory controller.

5. The method of claim 1 , wherein the at least one threshold value varies according to the cell charge state of the target cell.

6. The method of claim 5 , wherein the variation in threshold value with cell charge state of the target cell may be linear or may be determined by a mathematical function.

7. The method of claim 1 , wherein the at least one threshold value varies according to a length of time since the target cell was programmed with charge.

8. The method of claim 1 , wherein the at least one threshold value varies according to a total number of program and erase cycles the target cell has been subjected to.

9. The method of claim 1 , further comprising:

counting, by the non-volatile memory controller, the number of times a LLR value in a particular location in the look-up table is used to assign a LLR to the at least one bit representing the charge state of a cell,

counting, by the non-volatile memory controller, the number of times the at least one bit representing the charge state of the cell was a specific value at a specific location in the look-up table;

calculating a new probability the at least one bit representing the charge state of the cell is the specific value; and

adjusting the LLR value at the specific location in the look-up table according to the new probability.

10. The method of claim 1 , wherein the non-volatile memory is a flash memory.

11. The method of claim 1 , wherein the non-volatile memory comprises any one of: single level cells (SLCs), multi-level cells (MLCs), triple level cells (TLCs) and quadruple level cells (QLCs).

12. The method of claim 1 , wherein the plurality of cells of the non-volatile memory is capable of being in any one of two, four, eight or sixteen cell charge states.

13. A non-volatile memory controller comprising for providing one or more log likelihood ratios (LLRs) of at least one bit representing a charge state of a target cell of a plurality of cells of a non-volatile memory for low-density parity check (LDPC) decoding, each of the plurality of cells capable of being in any one of a plurality of cell charge states, the controller comprising:

storing circuitry configured to store a look-up table comprising LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory;

translating circuitry configured to determine a cell charge state of the target cell and a cell charge state of at least one of a plurality of neighboring cells based on data bits read from the target cell and the at least one of a plurality of neighboring cells;

a comparator configured to:

calculate a value representative of the difference in at least one of a plurality of charge states of the target cell and the at least one of the plurality of neighboring cells, and

compare the calculated value with at least one predetermined threshold value representative of the degree of disturbance effect the charge state of the at least one of the plurality of neighboring cells has on the charge state of the target cell;

look-up circuitry configured to:

set at least one address bit of the look-up table if the calculated value exceeds the at least one threshold value,

extract a new LLR value from the look-up table using the at least one address bit, and

provide the new LLR value of the at least one bit representing a state of the target cell to the LDPC decoder.

14. The non-volatile memory controller of claim 13 , wherein the translating circuitry performs multiple reads on each target cell or neighboring cell at varying reference voltages to read the data bits.

15. The non-volatile memory controller of claim 13 , wherein the translating circuitry also assigns a numerical value to each of the plurality of cell charge states.

16. The non-volatile memory controller of claim 15 , wherein the plurality of cell charge states and their associated numerical values are stored in the non-volatile memory controller.

17. The non-volatile memory controller of claim 13 , wherein the at least one threshold value varies according to the cell charge state.

18. The non-volatile memory controller of claim 17 , wherein the variation in threshold value with cell state may be linear or may be determined by a mathematical function.

19. The non-volatile memory controller of claim 13 , wherein the at least one threshold value varies according to a length of time since the target cell was programmed with charge.

20. The non-volatile memory controller of claim 13 , wherein the at least one threshold value varies according to a total number of program and erase cycles the target cell has been subjected to.

21. The non-volatile memory controller of claim 13 , wherein the comparator is also configured to:

count the number of times a LLR value in a particular location in the look-up table is assigned a LLR to the at least one bit representing the charge state of cell;

count the number of times the at least one bit representing the charge state of the cell was at a specific value;

calculate a new probability the at least one bit representing the charge state of the cell is a specific value and

adjust the LLR value at the specific location in the look-up table according to the new probability.

22. The non-volatile memory controller of claim 13 , wherein the memory is a flash memory.

23. The non-volatile memory controller of claim 13 , wherein the non-volatile memory comprises any one of: single level cells (SLCs), multi-level cells (MLCs), triple level cells (TLCs) and quadruple level cells (QLCs).

24. The non-volatile memory controller of claim 13 , wherein the plurality of cells of the non-volatile memory is capable of being in any one of two, four, eight or sixteen cell charge states.