IP Library Granted Patent US 10,345,102
Granted Patent B2
US 10,345,102 · App. 15/305,222 · Granted Jul 9, 2019

Method for evaluating warpage of wafer and method for sorting wafer

Inventor: Hisayuki Saito (Shirakawa, JP)
Assignee: SHIN-ETSU HANDOTAI CO., LTD.
G01B21/20G01B21/30G03F7/20G03F7/70633G03F7/70783H01L22/12G01B2210/56H01L21/67288
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Quick Facts
Patent No.
US 10,345,102
App. No.
15/305,222
Granted
Jul 9, 2019
Kind
B2
Abstract

A method for evaluating warpage of a wafer, includes measuring the warpage of the wafer that is in a free state without suction and determining, from measured warpage data, a wafer warpage amount A between two points Q 1 and Q 2 and a wafer warpage amount B between two points R 1 and R 2 , the points Q 1 and Q 2 being located on a straight line passing through an arbitrary point P in a wafer plane and a distance “a” away from the point P, the points R 1 and R 2 being located on the same straight line and a distance “b” away from the point P, the distance “b” differing from the distance “a”, calculating, from the wafer warpage amount A and the wafer warpage amount B, a difference in wafer warpage amount at the point P, and evaluating the warpage on the basis of the difference in wafer warpage amount.

Claims (22)

1. A method for selecting a wafer that will not cause overlay failure when used in a photolithography device, the method comprising the steps of:

measuring warpage of the wafer that is in a free state without suction;

determining, from measured data of the warpage of the wafer, a wafer warpage amount A between two points Q 1 and Q 2 , the points Q 1 and Q 2 being located (i) on a straight line passing through an arbitrary point P in a wafer plane, and (ii) a distance “a” away from the point P;

determining, from the measured data of the warpage of the wafer, a wafer warpage amount B between two points R 1 and R 2 , the points R 1 and R 2 being located (i) on the same straight line, and (ii) a distance “b” away from the point P, the distance “b” differing from the distance “a”;

calculating, from the determined wafer warpage amount A and the determined wafer warpage amount B, a pin chuck warpage of the wafer, the pin chuck warpage being a difference in wafer warpage amount at the point P;

determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage; and

upon a determination that the wafer will not cause overlay failure, selecting the wafer to be used in the photolithography device.

2. The method according to claim 1 , wherein the distance “a” and the distance “b” range from 0.5 to 12.5 mm, and the distance “a” minus the distance “b” is 5 mm or more.

3. The method according to claim 1 , wherein the wafer warpage amounts are determined from a height of a front surface of the wafer at the point P, assuming that a height of a back surface of the wafer is 0 at two points a certain distance away from the point P.

4. The method according to claim 2 , wherein the wafer warpage amounts are determined from a height of a front surface of the wafer at the point P, assuming that a height of a back surface of the wafer is 0 at two points a certain distance away from the point P.

5. The method according to claim 1 , wherein calculating the pin chuck warpage includes calculating differences in wafer warpage amount at least at a plurality of arbitrary points on an X-axis and a Y-axis perpendicularly intersecting at a center of the wafer plane.

6. The method according to claim 2 , wherein calculating the pin chuck warpage includes calculating differences in wafer warpage amount at least at a plurality of arbitrary points on an X-axis and a Y-axis perpendicularly intersecting at a center of the wafer plane.

7. The method according to claim 3 , wherein calculating the pin chuck warpage includes calculating differences in wafer warpage amount at least at a plurality of arbitrary points on an X-axis and a Y-axis perpendicularly intersecting at a center of the wafer plane.

8. The method according to claim 4 , wherein calculating the pin chuck warpage includes calculating differences in wafer warpage amount at least at a plurality of arbitrary points on an X-axis and a Y-axis perpendicularly intersecting at a center of the wafer plane.

9. The method according to claim 1 , wherein determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage includes: determining a relationship between pin chuck warpage and a presence of an occurrence of overlay failure.

10. The method according to claim 2 , wherein determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage includes: determining a relationship between pin chuck warpage and a presence of an occurrence of overlay failure.

11. The method according to claim 3 , wherein determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage includes: determining a relationship between pin chuck warpage and a presence of an occurrence of overlay failure.

12. The method according to claim 4 , wherein determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage includes: determining a relationship between pin chuck warpage and a presence of an occurrence of overlay failure.

13. The method according to claim 5 , wherein determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage includes: determining a relationship between pin chuck warpage and a presence of an occurrence of overlay failure.

14. The method according to claim 6 , wherein determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage includes: determining a relationship between pin chuck warpage and a presence of an occurrence of overlay failure.

15. The method according to claim 7 , wherein determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage includes: determining a relationship between pin chuck warpage and a presence of an occurrence of overlay failure.

16. The method according to claim 8 , wherein determining whether the wafer will cause overlay failure based on the calculated pin chuck warpage includes: determining a relationship between pin chuck warpage and a presence of an occurrence of overlay failure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SAITO, HISAYUKI
To: SHIN-ETSU HANDOTAI CO., LTD
Reel/Frame 040063/0946 →
Priority Claims (1)
JP 2014-094469 · May 1, 2014 · national
Continuity (1)
Related Publication 20170038202A1 · Feb 9, 2017
Cited By (1)
US 12,713,872