Dummy circuit and drive circuit for flat panel display device
View Patent ↗A dummy circuit and a driving circuit of a flat panel display device is provided in the present application, including: a plurality of dummy scanning lines extending in a row direction and separated from each other; a plurality of data lines extending in a column direction and separated from each other, the plurality of data lines including an outer dummy data line in the outermost side; the dummy scanning lines intersecting with the dummy data lines to form a plurality of dummy pixel regions, dummy pixel electrodes provided in the dummy pixel regions; a plurality of thin film transistors connecting the pixel electrode to the corresponding dummy scanning lines and the dummy data lines; and wherein the outer dummy data line corresponding to at least one end portion of the of the dummy scanning line outwardly avoidance disposed to make the projections of the both staggered.
1. A dummy circuit of a flat panel display device, comprising:
a plurality of dummy scanning lines extending in a row direction and separated from each other;
a plurality of dummy data lines extending in a column direction and separated from each other, the dummy data lines comprising an outer dummy data line in the outermost side; the dummy scanning lines intersecting with the dummy data lines to form a plurality of dummy pixel regions, dummy pixel electrodes provided in the dummy pixel regions;
a plurality of thin film transistors connecting the pixel electrode to the corresponding dummy scanning lines and the dummy data lines; and
wherein the outer dummy data line corresponding to at least one end portion of the of the dummy scanning line is outwardly avoidance disposed to make the projections of the both staggered,
wherein the outer dummy data line comprises a longitudinal portion and an avoidance portion, the longitudinal portion is connected to the avoidance portion, and the avoidance portion is located on the outer side of the longitudinal portion,
wherein with projection in the horizontal plane, a shortest distance between the avoidance portion and the end portion of the corresponding scanning line is in the range of 5 μm to 15 μm.
2. The dummy circuit of the flat panel display device according to claim 1 , wherein the avoidance portion is a fold line bent outwardly.
3. The dummy circuit of the flat panel display device according to claim 1 wherein the avoidance portion is a curved portion bent outwardly.
4. The dummy circuit of the flat panel display device according to claim 1 , wherein the outer dummy data line corresponding to all of end portions of the dummy scanning lines are outwardly avoidance disposed.
5. The dummy circuit of the flat panel display device according to claim 1 , wherein the outer dummy data line corresponding to all of end portions of the dummy scanning lines are outwardly avoidance disposed.
6. The dummy circuit of the flat panel display device according to claim 1 , wherein an insulating layer is disposed between the dummy scanning lines and the dummy data lines.
7. The dummy circuit of the flat panel display device according to claim 1 , wherein end portions of the dummy scanning lines are pointed ends.
8. The dummy circuit of the flat panel display device according to claim 1 , wherein the thin film transistors are low-temperature-polycrystalline-silicon (LTPS) based thin film transistor.
9. A driving circuit of a flat panel display device, comprising a dummy circuit of a flat panel display device, the dummy circuit of the flat panel display device comprising:
a plurality of dummy scanning lines extending in a row direction and separated from each other;
a plurality of dummy data lines extending in a column direction and separated from each other, the dummy data lines comprising an outer dummy data line in the outermost side; the dummy scanning lines intersecting with the dummy data lines to form a plurality of dummy pixel regions, dummy pixel electrodes provided in the dummy pixel regions;
a plurality of thin film transistors connecting the pixel electrode to the corresponding dummy scanning lines and the dummy data lines; and
wherein the outer dummy data line corresponding to at least one end portion of the of the dummy scanning line is outwardly avoidance disposed to make the projections of the both staggered,
wherein the outer dummy data line comprises a longitudinal portion and an avoidance portion, the longitudinal portion is connected to the avoidance portion, and the avoidance portion is located on the outer side of the longitudinal portion,
wherein with projection in the horizontal plane, a shortest distance between the avoidance portion and the end portion of the corresponding scanning line is in the range of 5 μm to 15 μm.
10. The driving circuit of the flat panel display device according to claim 9 , wherein the avoidance portion is a fold line bent outwardly.
11. The driving circuit of the flat panel display device according to claim 9 , wherein the avoidance portion is a curved portion bent outwardly.
12. The driving circuit of the flat panel display device according to claim 9 , wherein the outer dummy data line corresponding to all of end portions of the dummy scanning lines are outwardly avoidance disposed.
13. The driving circuit of the flat panel display device according to claim 9 , wherein the outer dummy data line corresponding to all of end portions of the dummy scanning lines are outwardly avoidance disposed.
14. The driving circuit of the flat panel display device according to claim 9 , wherein an insulating layer is disposed between the dummy scanning lines and he dummy data lines.
15. The driving circuit of the flat panel display device according to claim 9 , wherein end portions of the dummy scanning lines are pointed ends.
16. The driving circuit of the flat panel display device according to claim 9 , wherein the thin film transistors are low-temperature-polycrystalline-silicon (LTPS) based thin film transistor.