Semiconductor devices and methods of manufacture

1. A method of manufacturing a metal-oxide gated transistor device, the method comprising:

providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with an n-type dopant;

implanting the semiconductor layer with a p-type dopant using a single implantation mask and a substantially similar implantation dose including one or more implantation process sub-steps to simultaneously form a p-well region comprising a channel region, and a junction termination extension (JTE) of the metal-oxide gated transistor device in the semiconductor layer; wherein the implantation dose is in a range from about 2×10 13 cm 2 to about 12×10 13 cm −2 , and wherein a dopant concentration in the p-well region is substantially the same as the dopant concentration in the JTE; and

forming a p+-region in the semiconductor layer after the step of forming the p-well region and the JTE such that the p-well region is connected to the JTE via the p+-region, wherein the single implantation mask has a variable open window density that varies as a function of laterally increasing distance from a primary blocking junction of the semiconductor layer to the JTE.

2. The method of claim 1 , wherein the window regions further comprise a region defining the primary blocking junction in the semiconductor layer, and wherein the variable open window density of the window regions decreases laterally in a direction away from the region defining the primary blocking junction.

3. The method of claim 2 , wherein an open window density at the region defining the primary blocking junction is less than 80 percent.

4. The method of claim 2 , wherein the variable open window density of the window regions varies laterally such that an effective implanted dose varies in a range from about 80 percent at the primary blocking junction to about 10 percent of the total implanted dose at a terminal portion of the JTE.

5. The method of claim 2 , wherein an open window density of the window regions varies laterally such that an effective implanted dose varies in a range from about 70 percent at the primary blocking junction to about 10 percent of the total implanted dose at a terminal portion of the JTE.

6. The method of claim 1 , wherein the implantation dose is in a range from about 2×10 13 cm −2 to about 7.5×10 13 cm −2 .

7. The method of claim 1 , wherein the implantation dose is in a range from about 2×10 13 cm −2 to about 5×10 13 cm −2 .

8. The method of claim 1 , wherein implanting the semiconductor layer with the p-type dopant is performed at one or more implantation energy in a range greater than 5 keV and less than 700 keV.

9. The method of claim 1 , wherein the JTE comprises a plurality of discrete regions that are separated from each other, and wherein the discrete regions in the JTE are doped with the p-type dopant, such that an effective doping profile of the JTE decreases in a direction away from an edge of the primary blocking junction.

10. The method of claim 1 , wherein the semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

11. The method of claim 1 , wherein the semiconductor device is an insulated-gate bipolar transistor (IGBT).

12. The method of claim 1 , wherein a single implantation dose is used in each one of the implantation process sub-steps.

13. A metal-oxide gated transistor device comprising:

a silicon carbide (SiC) substrate;

a semiconductor layer comprising silicon carbide disposed on the substrate, wherein the semiconductor layer comprises a first region, a p-well region including a channel of the metal-oxide gated transistor device, a p+-region, and a junction termination extension (JTE);

wherein the first region is doped with an n-type dopant to have n-type conductivity, and the p-well region and the JTE are doped with a p-type dopant to have a p-type conductivity, and the p-well region is connected to the JTE via the p+-region;

wherein an implanted dose in the p-well region and the JTE is in a range from about 2×10 13 cm −2 to about 12×10 13 cm −2 ; and

wherein a dopant concentration in the p-well region is substantially the same as the dopant concentration in the JTE.

14. The metal-oxide gated transistor device of claim 13 , wherein the JTE comprises a plurality of discrete regions that are separated from each other, and wherein the discrete regions in the JTE are doped with the p-type dopant, such that an effective doping profile of the JTE decreases in a direction away from an edge of a primary blocking junction of the semiconductor layer.

15. The metal-oxide gated transistor device of claim 13 , wherein the semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

16. The metal-oxide gated transistor device of claim 13 , wherein the channel has a length less than 0.7 μm.

17. A metal-oxide gated transistor device, comprising:

a substrate,

a semiconductor layer comprising silicon carbide disposed on the substrate, wherein the semiconductor layer comprises a first region, a p-well region including a channel of the metal-oxide gated transistor device, and a junction termination extension (JTE);

wherein the first region is doped with an n-type dopant to have n-type conductivity, and the p-well region and the JTE are doped with a p-type dopant to have a p-type conductivity, and the p-well region is connected to the JTE via a p+-region;

wherein an implanted dose in the p-well region and the JTE is in a range from about 2×10 13 cm −2 to about 7.5×10 13 cm −2 ; and

wherein a dopant concentration in the p-well region is substantially the same as the dopant concentration in the JTE.

18. The metal-oxide gated transistor device of claim 17 , wherein the JTE comprises a plurality of discrete regions that are separated from each other, and wherein the plurality of discrete regions in the JTE are doped with the p-type dopant, such that an effective doping profile of the JTE decreases in a direction away from an edge of a primary blocking junction of the semiconductor layer.

19. The metal-oxide gated transistor device of claim 17 , wherein the semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

20. The metal-oxide gated transistor device of claim 17 , wherein the channel has a length less than 0.7 μm.