Semiconductor device

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type;

an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer;

a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region;

a concentration reducing region of the second conductivity type that is formed in a boundary region between the impurity region and the terminal region and that reduces a concentration difference between the impurity region and the terminal region, a concentration ratio of a second conductivity type impurity concentration of the concentration reducing region with respect to the second conductivity type impurity concentration of the terminal region being 0.225 or more and 1.0 or less; and

a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region, the concentration reducing region and the terminal region.

2. The semiconductor device according to claim 1 , wherein the connection portion of the surface electrode has a connection end portion positioned on the terminal region.

3. The semiconductor device according to claim 1 , wherein the impurity region includes a connection region connected to the terminal region, and

the concentration reducing region is formed in the connection region of the impurity region.

4. The semiconductor device according to claim 1 , wherein a concentration ratio of a second conductivity type impurity concentration of the concentration reducing region with respect to the second conductivity type impurity concentration of the terminal region is 0.25 or more and 0.5 or less.

5. The semiconductor device according to claim 1 , wherein the terminal region is formed along the peripheral edge of the impurity region so as to surround the impurity region.

6. The semiconductor device according to claim 1 , wherein a bottom portion of the terminal region is formed at a position deeper than a bottom portion of the impurity region with respect to a thickness direction of the semiconductor layer.

7. The semiconductor device according to claim 1 , wherein the terminal region overlaps with the impurity region.

8. The semiconductor device according to claim 1 , further comprising:

an insulating layer that is formed on the semiconductor layer, that has an opening by which the impurity region and the terminal region are exposed, and that is formed such that an inner wall surface defining the opening is positioned on the terminal region;

wherein the surface electrode is connected to the impurity region and to the terminal region in the opening of the insulating layer.

9. The semiconductor device according to claim 8 , wherein the insulating layer is formed with a uniform thickness.

10. The semiconductor device according to claim 8 , wherein the surface electrode includes a drawn portion that is continuously drawn out from an inside of the opening onto the insulating layer.

11. The semiconductor device according to claim 1 , wherein a connection size of the connection portion of the surface electrode with respect to the terminal region is 30 μm or more and not more than a width of the terminal region.

12. The semiconductor device according to claim 1 , wherein a connection size of the connection portion of the surface electrode with respect to the terminal region is 60 μm or more and not more than a width of the terminal region.

13. The semiconductor device according to claim 1 , wherein the impurity region forms a pn junction portion between the semiconductor layer and the impurity region, and

a pn junction diode including the pn junction portion is formed in the semiconductor layer.

14. The semiconductor device according to claim 1 , further comprising:

an emitter region of the first conductivity type formed in the surface layer portion of the impurity region;

a collector region of the second conductivity type formed in the semiconductor layer so as to face a bottom portion of the impurity region with a partial region of the semiconductor layer interposed between the second conductivity type collector region and the bottom portion of the impurity region; and

a gate electrode formed on the semiconductor layer so as to face the impurity region with a gate insulating film interposed between the gate electrode and the impurity region;

wherein an IGBT in which the impurity region serves as a channel region is formed in the semiconductor layer.

15. The semiconductor device according to claim 1 , further comprising:

a source region of the first conductivity type formed in the surface layer portion of the impurity region;

a drain region of the first conductivity type formed in the semiconductor layer so as to face a bottom portion of the impurity region with a partial region of the semiconductor layer interposed between the drain region and the bottom portion of the impurity region; and

a gate electrode formed on the semiconductor layer so as to face the impurity region with a gate insulating film interposed between the gate electrode and the impurity region;

wherein a MISFET in which the impurity region serves as a channel region is formed in the semiconductor layer.

16. A semiconductor device comprising:

a semiconductor layer of a first conductivity type;

an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer;

a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region;

a concentration reducing region of the second conductivity type that is formed in a boundary region between the impurity region and the terminal region and that reduces a concentration difference between the impurity region and the terminal region, a concentration ratio of a second conductivity type impurity concentration of the concentration reducing region with respect to the second conductivity type impurity concentration of the terminal region being 0.225 or more and 1.0 or less; and

a surface electrode that is formed on the semiconductor layer and that is connected to the impurity region.

17. The semiconductor device according to claim 16 , wherein the impurity region includes a connection region connected to the terminal region, and

the concentration reducing region is formed in the connection region of the impurity region.

18. The semiconductor device according to claim 16 , wherein the surface electrode is connected to the concentration reducing region in addition to being connected to the impurity region.

19. The semiconductor device according to claim 16 , wherein a concentration ratio of a second conductivity type impurity concentration of the concentration reducing region with respect to the second conductivity type impurity concentration of the terminal region is 0.25 or more and 0.5 or less.

20. The semiconductor device according to claim 16 , wherein the surface electrode includes a connection portion connected to the impurity region, and

the connection portion of the surface electrode has a connection end portion positioned on the impurity region.

21. The semiconductor device according to claim 16 , further comprising:

an insulating layer that is formed on the semiconductor layer, that has an opening by which the impurity region is exposed, and that is formed such that an inner wall surface defining the opening is positioned on the impurity region;

wherein the surface electrode is connected to the impurity region in the opening of the insulating layer.