Wafer-scale integration of vacancy centers for spin qubits
Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.
1. A spin qubit device assembly comprising:
a substrate including a semiconductor material; and
at least one vacancy center (VC) island including an insulating carbon-based material having at least one VC,
wherein at least a portion of the VC island is surrounded by the semiconductor material.
2. The spin qubit device assembly according to claim 1 , wherein said portion of the VC island is integrated in an uppermost layer of the semiconductor material.
3. The spin qubit device assembly according to claim 1 , wherein said portion of the VC island extends into the semiconductor material to a depth between 20 nanometers and 1000 nanometers.
4. The spin qubit device assembly according to claim 1 , wherein a cross-section of said portion of the VC island in a first plane is larger than a cross-section of said portion of the VC island in a second plane, the second plane being further away from the uppermost surface of the substrate than the first plane.
5. The spin qubit device assembly according to claim 1 , wherein said portion of the VC island has a substantially conical shape or a substantially truncated cone shape.
6. The spin qubit device assembly according to claim 1 , further comprising a layer of a further material between the semiconductor material and said portion of the VC island, wherein the further material includes a material having hydroxyl group (OH) terminations, a material having hydrogen (—H) terminations, a material having oxygen (—O) terminations, or a material having nitrogen (—N) terminations, and has a thickness between 0.1 and 5 nanometers.
7. The spin qubit device assembly according to claim 1 , wherein said portion of the VC island is a first portion, the VC island further having a second portion that is not surrounded by the semiconductor material.
8. The spin qubit device assembly according to claim 1 , wherein at least a portion of an uppermost surface of the VC island has a convex shape.
9. The spin qubit device assembly according to claim 1 , wherein the insulating carbon-based material includes diamond.
10. The spin qubit device assembly according to claim 1 , wherein the insulating carbon-based material includes an isotopically purified carbon, wherein the isotopically purified carbon includes 13C isotopes in an amount less than 1 atomic-percent.
11. A quantum integrated circuit (IC) package, comprising:
a semiconductor substrate;
a first spin qubit and a second spin qubit, each comprising a vacancy center (VC) island that includes an insulating carbon-based material with a VC therein, wherein at least a portion of the VC island is surrounded by the semiconductor substrate;
a resonator associated with the first spin qubit; and
a resonator associated with the second spin qubit.
12. The quantum IC package according to claim 11 , wherein one end of the resonator associated with the first spin qubit is over at least a portion of the VC island of the first spin qubit.
13. The quantum IC package according to claim 12 , wherein said one end of the resonator associated with the first spin qubit overlaps with the at least a portion of the VC island by between 20 and 100 nanometers.
14. The quantum IC package according to claim 11 , further comprising:
a waveguide associated with the first spin qubit; and
a waveguide associated with the second spin qubit.
15. The quantum IC package according to claim 14 , wherein the waveguide associated with the first spin qubit and the waveguide associated with the second spin qubit form a beam splitter.
16. The quantum IC package according to claim 14 , wherein a portion of the waveguide associated with the first spin qubit is at a distance between 10 to 200 nanometers from a portion of the waveguide associated with the second spin qubit.
17. The quantum IC package according to claim 14 , wherein the waveguide associated with the first spin qubit comprises a structure to support propagation of zero-phonon-line (ZPL) emission.
18. The quantum IC package according to claim 14 , wherein a portion of the waveguide associated with the first spin qubit is at a distance between 10 to 200 nanometers from the resonator associated with the first spin qubit.
19. The quantum IC package according to claim 14 , wherein a portion of the waveguide associated with the first spin qubit is coupled to a photon detector.
20. The quantum IC package according to claim 11 , further comprising a first pair of electrodes to perform Stark tuning of a resonance frequency of the VC of the first spin qubit, and a second pair of electrodes to tune a resonance frequency of the resonator associated with the first spin qubit.
21. The quantum IC package according to claim 11 , further comprising a radiofrequency (RF) line to change a spin state of at least one of the first spin qubit and the second spin qubit.
22. The quantum IC package according to claim 11 , further comprising an IC element coupled to the semiconductor substrate by a plurality of interconnects, wherein the IC element is one of an interposer, a circuit board, a flexible board, or a package substrate.
23. A spin qubit device assembly comprising:
a semiconductor substrate;
a buffer layer over the substrate, the buffer layer comprising a III-N material; and
at least one vacancy center (VC) island including an insulating carbon-based material having at least one VC,
wherein the VC island is over or at least partially in the III-N material.
24. The spin qubit device assembly according to claim 23 , wherein a lattice constant of the semiconductor substrate is different from a lattice constant of the III-N material by at least 15%.
25. The spin qubit device assembly according to claim 23 , further comprising one or more structures of a dielectric material on the semiconductor substrate, where portions of the buffer layer enclose the one or more structures, and wherein where a ratio of an area of the semiconductor substrate that is in contact with the dielectric material to an area of the semiconductor substrate that is in contact with the III-N material is at least 1.
26. The spin qubit device assembly according to claim 23 , where at least a portion of the at least one VC island is in an uppermost layer of the III-N material.
27. The spin qubit device assembly according to claim 25 , where the portion of the at least one VC island extends into the III-N material to a depth between about 20 nanometers and 1000 nanometers.
28. The spin qubit device assembly according to claim 23 , further including a further layer of the insulating carbon-based material over the buffer layer and the at least one VC island is in the further layer.
29. The spin qubit device assembly according to claim 23 , where the insulating carbon-based material includes an isotopically purified carbon.
30. The spin qubit device assembly according to claim 29 , where the isotopically purified carbon includes 13C isotopes in an amount less than about 1 atomic-percent.
31. A quantum computing device, comprising:
a quantum processing device comprising a plurality of spin qubits; and
a memory, configured to store data generated by the plurality of spin qubits during operation of the quantum processing device,
wherein:
the quantum processing device includes a spin qubit device assembly that includes a semiconductor material, and
each of the plurality of spin qubits comprises a vacancy center (VC) island that includes an insulating carbon-based material having at least one VC, wherein the VC island is over or at least partially in the semiconductor material.
32. The quantum computing device according to claim 31 , wherein the semiconductor material is a III-N material.
33. The quantum computing device according to claim 32 , wherein:
the III-N material is a first semiconductor material,
the spin qubit device assembly further includes a second semiconductor material,
the first semiconductor material is over the second semiconductor material, and
a lattice constant of the second semiconductor material is different from a lattice constant of the III-N material by at least 15%.
34. The quantum computing device according to claim 31 , wherein the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
35. The quantum computing device according to claim 31 , wherein a cross-section of the portion of the VC island in a first plane is larger than a cross-section of said portion of the VC island in a second plane.