IP Library › Granted Patent US 10,348,085
Granted Patent B2
US 10,348,085 · App. 15/243,791 · Granted Jul 9, 2019

Static electricity protection circuit, semiconductor integrated circuit device, and electronic apparatus

Inventor: Masuhide Ikeda (Matsumoto, JP)
Assignee: SEIKO EPSON CORPORATION
H02H9/046H01L27/0255H01L27/0262H01L27/0266H01L27/0288
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Quick Facts
Patent No.
US 10,348,085
App. No.
15/243,791
Granted
Jul 9, 2019
Kind
B2
Abstract

This static electricity protection circuit starts a discharge operation only if an applied voltage is greater than or equal to a set voltage, and protects a discharge circuit also when noise or the like is applied during a normal operation. This static electricity protection circuit includes: a resistor R 1 and clamp circuit that are connected in series between nodes N 1 and N 2 ; a first transistor that turns on in accordance with an increase in a potential difference generated in the resistor R 1 ; a resistor R 2 and capacitor C 2 that are connected via a node N 4 between the nodes N 1 and N 2 ; a second transistor that is connected in series with the first transistor between the nodes N 1 and N 5 ; a resistor R 3 connected between the nodes N 5 and N 2 ; a third transistor connected between the nodes N 4 and N 2 ; and a discharge circuit connected between the nodes N 1 and N 2.

Claims (49)

1. A static electricity protection circuit that is connected to a first terminal via a first node and is connected to a second terminal via a second node, comprising:

a first impedance element connected between one of the first and second nodes and a third node;

a first clamp circuit connected between the third node and the other of the first and second nodes;

a first transistor configured to turn on in accordance with an increase in a potential difference generated between two ends of the first impedance element when the first node reaches a higher potential than the second node;

a second impedance element connected between the one of the first and second nodes and a fourth node;

a capacitor or second clamp circuit connected between the fourth node and the other of the first and second nodes;

a second transistor that is connected in series with the first transistor between the one of the first and second nodes and a fifth node, and is configured to turn on in accordance with an increase in a potential difference generated between two ends of the second impedance element when the first node reaches a higher potential than the second node;

a third impedance element connected between the fifth node and the other of the first and second nodes;

a third transistor that is connected between the fourth node and the other of the first and second nodes, and is configured to turn on in accordance with an increase in a potential difference generated between two ends of the third impedance element when the first node reaches a higher potential than the second node; and

a discharge circuit that is connected between the first node and the second node and is configured to allow current to flow from the first node to the second node in accordance with an increase in a potential difference generated between the two ends of the second or third impedance element when the first node reaches a higher potential than the second node.

2. A static electricity protection circuit that is connected to a first terminal via a first node and is connected to a second terminal via a second node, comprising:

a first clamp circuit connected between one of the first and second nodes and a third node;

a first impedance element connected between the third node and the other of the first and second nodes;

a first transistor configured to turn on in accordance with an increase in a potential difference generated between two ends of the first impedance element when the first node reaches a higher potential than the second node;

a second impedance element connected between the one of the first and second nodes and a fourth node;

a capacitor or second clamp circuit connected between the fourth node and the other of the first and second nodes;

a second transistor that is connected between the one of the first and second nodes and a fifth node, and is configured to turn on in accordance with an increase in a potential difference generated between two ends of the second impedance element when the first node reaches a higher potential than the second node;

a third impedance element connected between the fifth node and the other of the first and second nodes;

a third transistor that is connected in series with the first transistor between the fourth node and the other of the first and second nodes, and is configured to turn on in accordance with an increase in a potential difference generated between two ends of the third impedance element when the first node reaches a higher potential than the second node; and

a discharge circuit that is connected between the first node and the second node and is configured to allow current to flow from the first node to the second node in accordance with an increase in a potential difference generated between the two ends of the second or third impedance element when the first node reaches a higher potential than the second node.

3. The static electricity protection circuit according to claim 1 , further comprising

a fourth impedance element connected between the fifth node and the sixth node,

wherein the third impedance element is connected between the sixth node and the other of the first and second nodes.

4. The static electricity protection circuit according to claim 2 , further comprising a second capacitor connected in parallel with the first clamp circuit.

5. The static electricity protection circuit according to claim 1 , wherein a breakdown voltage of the discharge circuit is higher than a clamp voltage of the first clamp circuit and higher than a clamp voltage of the second clamp circuit.

6. The static electricity protection circuit according to claim 1 , wherein the first and second clamp circuits include a transistor having an impurity diffusion region of a first conductivity type, and the discharge circuit includes a transistor having an impurity diffusion region of a second conductivity type.

7. The static electricity protection circuit according to claim 1 , wherein the discharge circuit includes a transistor and a thyristor connected in series.

8. The static electricity protection circuit according to claim 1 , wherein the discharge circuit includes a plurality of transistors connected in series.

9. The static electricity protection circuit according to claim 1 , wherein the discharge circuit includes a transistor and a diode connected in series.

10. The static electricity protection circuit according to claim 2 , further comprising

a fourth impedance element connected between the fifth node and the sixth node,

wherein the third impedance element is connected between the sixth node and the other of the first and second nodes.

11. The static electricity protection circuit according to claim 10 , further comprising a second capacitor connected in parallel with the first clamp circuit.

12. The static electricity protection circuit according to claim 2 , wherein a breakdown voltage of the discharge circuit is higher than a clamp voltage of the first clamp circuit and higher than a clamp voltage of the second clamp circuit.

13. The static electricity protection circuit according to claim 2 , wherein the first and second clamp circuits include a transistor having an impurity diffusion region of a first conductivity type, and the discharge circuit includes a transistor having an impurity diffusion region of a second conductivity type.

14. The static electricity protection circuit according to claim 2 , wherein the discharge circuit includes a transistor and a thyristor connected in series.

15. The static electricity protection circuit according to claim 2 , wherein the discharge circuit includes a plurality of transistors connected in series.

16. The static electricity protection circuit according to claim 2 , wherein the discharge circuit includes a transistor and a diode connected in series.

17. A static electricity protection circuit that is connected to a first terminal via a first node and is connected to a second terminal via a second node, comprising:

a discharge circuit connected between the first node and the second node;

a latch circuit configured to latch and output a signal for causing the discharge circuit to operate when static electricity is applied to the first or second terminal;

a switch circuit configured to control the latch circuit; and

a control circuit configured to cause the latch circuit to operate by turning on the switch circuit in a case where a voltage applied between the first node and the second node is greater than or equal to a predetermined voltage, the control circuit including:

a first impedance element connected between one of the first and second nodes and a third node,

a first transistor configured to turn on in accordance with an increase in a potential difference generated between two ends of the first impedance element when the first node reaches a higher potential than the second node, and

a second transistor connected in series with the first transistor between the one of the first and second nodes and a fifth node, and is configured to turn on in response to the voltage applied between the first node and the second node being greater than or equal to the predetermined voltage.

18. A semiconductor integrated circuit device comprising the static electricity protection circuit according to claim 1 .

19. A semiconductor integrated circuit device comprising the static electricity protection circuit according to claim 9 .

20. An electronic apparatus comprising the semiconductor integrated circuit device according to claim 18 .

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY TYPE FROM APPLICATION NO. 10348085 TO PATENT NO. 10348085 PREVIOUSLY RECORDED ON REEL 69852 FRAME 424. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 15, 2025
From: SEMPERIS TECHNOLOGIES INC.
To: SEMPERIS LTD.
Reel/Frame 069933/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2025
From: SEMPERIS TECHNOLOGIES INC.
To: SEMPERIS LTD.
Reel/Frame 069852/0424 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2016
From: IKEDA, MASUHIDE
To: SEIKO EPSON CORPORATION
Reel/Frame 039501/0297 →
Priority Claims (1)
JP 2015-171729 · Sep 1, 2015 · national
Continuity (1)
Related Publication 20170063080A1 · Mar 2, 2017