IP Library › Granted Patent US 10,348,406
Granted Patent B2
US 10,348,406 · App. 15/198,041 · Granted Jul 9, 2019

Electrical interface module

Inventors: Chungang Zhang (Qingdao, CN); Shu Liu (Qingdao, CN); Liang Shi (Qingdao, CN); Hua Zhang (Qingdao, CN)
Assignee: Hisense Broadband Multimedia Technologies, Ltd.
H04B10/2504H04B10/0731H04B10/27G01M11/3136G01M11/3145H04B10/071H04B10/0771H04B10/0775H04B10/40H04L41/145H04L43/50H04Q11/0067
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,348,406
App. No.
15/198,041
Granted
Jul 9, 2019
Kind
B2
Abstract

This disclosure provides an electrical interface module including a signal processor, a switch, and a connection component, wherein the signal processor includes a first interface, a second interface, and a third interface; the first interface and the second interface of the signal processor are connected with the connection component through the switch, and configured to output differential signals; the third interface of the signal processor is connected with the switch, and configured to output an enable signal; and the switch is configured to be controlled by the enable signal to be closed so that the differential signals are output through the connection component.

Claims (43)

1. An electrical interface module, connectable to an Optical Line Terminal (OLT) device, comprising a signal processor, a switch, and a connection component, wherein:

the signal processor comprises a first interface, a second interface, and a third interface;

the first interface and the second interface of the signal processor are connected with the connection component through the switch, and configured to output differential signals processed by the signal processor;

the third interface of the signal processor is connected with the switch, and configured to output an enable signal; and

the switch is configured to be controlled by the enable signal to be conductive to enable the processed differential signals to be transmitted to the connection component so that the processed differential signals are output through the connection component.

2. The electrical interface module according to claim 1 , wherein the switch is a limiting amplifier, and the signal processor is a Medium Access Controller (MAC); and

the third interface of the MAC is connected with an enable (EN) port of the limiting amplifier, and configured to transmit an enable signal to the limiting amplifier to control the limiting amplifier to output the processed differential signals.

3. The electrical interface module according to claim 1 , further comprising an XOR logical gate circuit, wherein:

the signal processor further comprises a sixth interface;

the XOR logical gate circuit comprises a first interface, a second interface, and a third interface;

the third interface of the signal processor is connected with the first interface of the XOR logical gate circuit;

the sixth interface of the signal processor is connected with the second interface of the XOR logical gate circuit;

the third interface of the XOR logical gate circuit is connected with the connection component; and

the signal processor outputs an SD signal or an LOS signal through the XOR logical gate circuit.

4. The electrical interface module according to claim 3 , wherein a first resistor is connected between the sixth interface of the signal processor, and the second interface of the XOR logical gate circuit.

5. The electrical interface module according to claim 1 , further comprising an XOR logical gate circuit and a Micro Controller Unit (MCU), wherein:

the XOR logical gate circuit comprises a first interface, a second interface, and a third interface;

the MCU comprises a first interface;

the third interface of the signal processor is connected with the first interface of the XOR logical gate circuit;

the first interface of the MCU is connected with the second interface of the XOR logical gate circuit;

the third interface of the XOR logical gate circuit is connected with the connection component; and

the MCU outputs an SD signal or an LOS signal through the XOR logical gate circuit.

6. The electrical interface module according to claim 5 , wherein a second resistor is connected between the first interface of the MCU, and the second interface of the XOR logical gate circuit.

7. The electrical interface module according to claim 5 , wherein the MCU further comprises a second interface, a third interface, a fourth interface, and a fifth interface; and

the second interface of the MCU, the third interface of the MCU, the fourth interface of the MCU, and the fifth interface of the MCU are connected respectively with the connection component.

8. The electrical interface module according to claim 2 , further comprising a level converter, wherein:

the level converter comprises a first interface, a second interface, a third interface, and a fourth interface;

the limiting amplifier comprises a first interface, a second interface, a third interface, and a fourth interface;

the first interface of the signal processor is connected with the first interface of the level converter, and the second interface of the signal processor is connected with the second interface of the level converter;

the third interface of the level converter is connected with the first interface of the limiting amplifier;

the fourth interface of the level converter is connected with the second interface of the limiting amplifier;

the third interface and the fourth interface of the limiting amplifier are connected respectively with the connection component; and

the level converter is configured to convert levels of the signal output by the signal processor into levels receivable by the limiting amplifier.

9. The electrical interface module according to claim 8 , wherein a third resistor is connected between the first interface and the second interface of the level converter;

a first ground resistor is connected with the third interface of the level converter, and a second ground resistor is connected with the fourth interface of the level converter;

a fourth resistor is connected between the third interface of the level converter, and the first interface of the limiting amplifier, and a fifth resistor is connected between the fourth interface of the level converter, and the second interface of the limiting amplifier; and

a sixth resistor is connected between the first interface and the second interface of the limiting amplifier.

10. The electrical interface module according to claim 1 , wherein the signal processor further comprises a fourth interface and a fifth interface;

the fourth interface and the fifth interface of the signal processor are connected with the connection component, and configured to receive differential signals from the OLT device; and

a first capacitor is connected between the fourth interface of the signal processor, and the connection component, and a second capacitor is connected between the fifth interface of the signal processor, and the connection component.

11. The electrical interface module according to claim 1 , wherein the electrical interface module is connected to the OLT device through the connection component, and the connection component is configured to output the processed differential signals to the OLT device.

12. The electrical interface module according to claim 1 , wherein the electrical interface module is all electrical.

13. The electrical interface module according to claim 1 , wherein the electrical interface module does not involve processing of an optical signal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2017
From: HISENSE USA CORPORATION; HISENSE INTERNATIONAL CO., LTD.
To: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES, LTD.
Reel/Frame 043143/0788 →
ASSIGNMENT OF AN UNDIVIDED INTEREST Recorded Mar 8, 2017
From: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES CO., LTD.
To: HISENSE USA CORPORATION; HISENSE INTERNATIONAL CO., LTD.
Reel/Frame 041909/0527 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2016
From: ZHANG, CHUNGANG; LIU, SHU; SHI, LIANG; ZHANG, HUA
To: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES, LTD.
Reel/Frame 039057/0973 →
Priority Claims (1)
CN 2015 1 0589882 · Sep 16, 2015 · national
Continuity (1)
Related Publication 20170078021A1 · Mar 16, 2017