IP Library Granted Patent US 10,348,992
Granted Patent B2
US 10,348,992 · App. 15/961,584 · Granted Jul 9, 2019

Comparator, ad converter, solid-state imaging device, electronic apparatus, and method of controlling comparator

Inventors: Masaki Sakakibara (Kanagawa, JP); Kenichi Aoyagi (Kanagawa, JP); Seiji Yamada (Kanagawa, JP)
Assignee: Sony Corporation
H04N5/3745H01L27/1461H01L27/1464H01L27/14612H01L27/14621H01L27/14627H01L27/14634H01L27/14636H01L27/14645H03K5/24H03K5/2481H04N5/378H04N5/379H04N5/37455
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Quick Facts
Patent No.
US 10,348,992
App. No.
15/961,584
Granted
Jul 9, 2019
Kind
B2
Abstract

The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.

Claims (4)

1. A comparator comprising:

a comparison unit configured to output a comparison result signal based on a comparison of a voltage of an input signal with a voltage of a reference signal, wherein the comparison unit includes at least a first transistor to which the input signal is input and at least a second transistor to which the reference signal is input, wherein the first transistor is connected to a floating diffusion layer of a pixel circuit, and wherein the voltage of the reference signal is set at a predetermined voltage to reset the floating diffusion layer of the pixel circuit;

a positive feedback circuit configured to increase a speed of transition when the comparison result signal is inverted, wherein when the comparison result signal is inverted a code input signal is stored in a storage unit; and

a current limiting unit configured to limit a current flowing in the comparison unit after an inversion of the comparison result signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2020
From: SAKAKIBARA, MASAKI; AOYAGI, KENICHI; YAMADA, SEIJI
To: SONY CORPORATION
Reel/Frame 053563/0103 →
Priority Claims (1)
JP 2014-144389 · Jul 14, 2014 · national
Continuity (2)
Continuation 14916652
Related Publication 20180241960A1 · Aug 23, 2018