Semiconductor device
An assist driver is coupled to an end of a word line to which a word line driver is not coupled, and couples the other end of the word line to a first power source, in accordance with a voltage of the other end of the word line.
1. A semiconductor device comprising:
a memory array which includes a plurality of memory cells arranged in a matrix;
a plurality of word lines which are provided respectively in rows of the plurality of memory cells;
a word line driver which is coupled to an end of a first word line of the plurality of word lines, and which is configured to couple the end of the first word line to a first power source in accordance with a select signal transmitted by an address decoder; and
an assist driver which is coupled to the other end of the first word line,
wherein the assist driver includes:
a PMOS transistor having a source coupled with a second power source and having a drain coupled with the other end of the first word line; and
a NAND circuit having one input coupled to the other end of the first word line, another input receiving a control signal pulse, and an output coupled to a gate of the PMOS transistor,
wherein a signal wiring is arranged on an outside of the memory array, and
wherein the control signal pulse is transmitted to the NAND circuit through the signal wiring.
2. The semiconductor device according to claim 1 ,
wherein the control signal pulse is at a high level in a period from a rising start time of the word line until a voltage of the other end of the word line reaches a voltage of the first power source, and the pulse is at a low level in a period from a falling start time of the word line until the voltage of the other end of the word line reaches a ground voltage.
3. The semiconductor device according to claim 1 ,
wherein the first power source and the second power source are supplied with a same voltage.
4. A semiconductor device comprising:
a memory array which includes:
a plurality of memory cells arranged in a matrix;
a plurality of word lines which are provided respectively in the rows of the plurality of memory cells;
a word line driver which is coupled to an end of a first word line of the plurality of word lines, and which is configured to couple the end of the first word line to a first power source in accordance with a select signal transmitted by an address decoder; and
an assist driver which is coupled to the other end of the first word line,
wherein the assist driver includes:
a PMOS transistor having a source coupled with a second power source and having a drain coupled with the other end of the first word line; and
a delay circuit coupled to the other end of the first word line and a NAND circuit having one input coupled to the other end of the first word line, another input receiving an output of the delay circuit, and an output coupled to a gate of the PMOS transistor.
5. The semiconductor device according to claim 4 ,
wherein the delay circuit includes an odd number of inverters coupled in series.
6. The semiconductor device according to claim 4 ,
wherein the first power source and the second power source are supplied with a same voltage.
7. A semiconductor device comprising:
a memory array which includes a plurality of memory cells arranged in a matrix;
a plurality of word lines which are provided respectively in rows of the plurality of memory cells;
a word line driver which is coupled to an end of a first word line of the plurality of word lines, and which is configured to couple the end of the first word line to a first power source in accordance with a select signal transmitted by an address decoder; and
an assist driver which is coupled to the other end of the first word line,
wherein the word line driver includes an inverter whose output is coupled to the end of a first word line, and
wherein the assist driver includes:
a PMOS transistor having a source coupled with a second power source and having a drain coupled with the other end of the first word line; and
a delay circuit coupled to the other end of the first word line and a NAND circuit having one input coupled to the other end of the first word line, another input receiving an output of the delay circuit, and an output coupled to a gate of the PMOS transistor.
8. The semiconductor device according to claim 7 ,
wherein each of the memory cells is an SRAM.
9. The semiconductor device according to claim 8 ,
wherein each of the memory cells is a laterally long cell.
10. The semiconductor device according to claim 7 , further comprising:
a bit line pair which is provided respectively in columns of the plurality of memory cells,
wherein a write driver is coupled to the bit line pair of a plurality of adjacent columns, and outputs a voltage in accordance with written data to a bit line pair of a selected column from the adjacent columns, at time of writing data to the memory cell.
11. The semiconductor device according to claim 7 , further comprising:
a bit line pair which is arranged respectively in columns of the plurality of memory cells; and
a sense amplifier which is coupled to a bit line pair of adjacent columns and amplifies a voltage of a bit line pair of a selected column from the adjacent columns, at time of reading data from the memory cell.
12. The semiconductor device according to claim 7 ,
wherein the delay circuit includes an odd number of inverters coupled in series.