IP Library › Granted Patent US 10,354,955
Granted Patent B2
US 10,354,955 · App. 15/687,362 · Granted Jul 16, 2019

Graphene as interlayer dielectric

Inventors: Ye Lu (San Diego, CA); Bin Yang (San Diego, CA); Junjing Bao (San Diego, CA)
Assignee: QUALCOMM Incorporated
H01L23/53295C01B32/182H01L21/02115H01L21/02227H01L21/02321H01L21/02362H01L21/31111H01L21/76802H01L21/76822H01L21/76829H01L23/528H01L23/5226H01L23/5329H01L21/02271H01L21/76831H01L21/76877H01L21/823493H01L23/5222H01L23/53228H01L29/78H01L29/7851
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Quick Facts
Patent No.
US 10,354,955
App. No.
15/687,362
Granted
Jul 16, 2019
Kind
B2
Abstract

An integrated circuit may include multiple back-end-of-line (BEOL) interconnect layers. The BEOL interconnect layers may include conductive lines and conductive vias. The integrated circuit may further include an interlayer dielectric (ILD) between the BEOL interconnect layers. The ILD may include the conductive lines and the conductive vias. At least a portion of the ILD may include a low-K insulating graphene alloy.

Claims (32)

1. An integrated circuit, comprising:

a plurality of back-end-of-line (BEOL) interconnect layers comprising conductive lines and conductive vias; and

a low-K interlayer dielectric (ILD) between the BEOL interconnect layers including the conductive lines and the conductive vias, in which the low-K ILD comprises a low-K dielectric fill material and a low-K insulating graphene alloy, disposed in alternating thin layers of the low-K dielectric fill material on the low-K insulating graphene alloy, each surrounding the plurality of BEOL interconnect layers.

2. The integrated circuit of claim 1 , in which the low-K insulating graphene alloy comprises fluorographene, oxidized graphene, or hydrogenated graphene.

3. The integrated circuit of claim 1 , in which the alternating layers have different thicknesses.

4. The integrated circuit of claim 1 , in which the alternating layers have similar thicknesses.

5. The integrated circuit of claim 1 , in which the conductive lines and the vias of the BEOL interconnect layers are at least partially lined with a conformal dielectric liner.

6. The integrated circuit of claim 5 , in which the conformal dielectric liner comprises SiN x .

7. The integrated circuit of claim 1 , integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

8. A method of making an integrated circuit, comprising:

patterning and etching a low-K insulating graphene alloy layer on a middle-of-line (MOL) layer of the integrated circuit by

depositing a sacrificial catalyst layer on the MOL layer;

diffusing a low resistivity carbon alloy through the sacrificial catalyst layer;

removing the sacrificial catalyst layer; and

fluorinating the low resistivity carbon alloy; and

forming back-end-of-line (BEOL) interconnect layers including conductive lines and conductive vias in the patterned low-K insulating graphene alloy layer.

9. The method of claim 8 , further comprising growing a low-K dielectric layer on the MOL layer of the integrated circuit.

10. The method of claim 8 , further comprising depositing a low-K dielectric layer on an active layer of the integrated circuit.

11. The method of claim 8 , in which the low-K insulating graphene alloy layer comprises fluorographene, oxidized graphene, or hydrogenated graphene.

12. The method of claim 8 , in which the low resistivity carbon alloy comprises graphene.

13. The method of claim 8 , in which the integrated circuit is integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

14. A method of making an integrated circuit, comprising:

patterning and etching a low-K insulating graphene alloy layer on a middle-of-line (MOL) layer of the integrated circuit by:

depositing a thin catalyst layer on the MOL layer;

decomposing carbonaceous precursors from the thin catalyst layer; and

fluorinating a low resistivity carbon alloy; and

forming back-end-of-line (BEOL) interconnect layers including conductive lines and conductive vias in the patterned low-K insulating graphene alloy layer.

15. An integrated circuit, comprising:

a plurality of back-end-of-line (BEOL) interconnect layers comprising means for conducting; and

a low-K interlayer dielectric (ILD) between the BEOL interconnect layers including the means for conducting, in which the low-K ILD comprises a low-K dielectric material and a low-K insulating graphene alloy, disposed in alternating thin layers of the low-K dielectric fill material on the low-K insulating graphene alloy, each surrounding the plurality of BEOL interconnect layers.

16. The integrated circuit of claim 15 , in which the low-K insulating graphene alloy comprises fluorographene, oxidized graphene, or hydrogenated graphene.

17. The integrated circuit of claim 15 , integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2017
From: LU, YE; YANG, BIN; BAO, JUNJING
To: QUALCOMM INCORPORATED
Reel/Frame 043758/0298 →
Continuity (2)
Provisional Application 62522024 · Jun 19, 2017
Related Publication 20180366413A1 · Dec 20, 2018