IP Library › Granted Patent US 10,359,831
Granted Patent B2
US 10,359,831 · App. 15/447,866 · Granted Jul 23, 2019

Cache power management

Inventors: Ashley John Crawford (Cambridge, GB); Andrew Christopher Rose (Cambridge, GB); Tessil Thomas (Cambridge, GB); David Guillen Fandos (Cambridge, GB)
Assignee: ARM Limited
G06F1/3275G06F1/3225G06F1/3287G06F1/3296Y02D10/13Y02D10/14
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Quick Facts
Patent No.
US 10,359,831
App. No.
15/447,866
Granted
Jul 23, 2019
Kind
B2
Abstract

A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

Claims (41)

1. A method of operating a cache comprising the steps of:

calculating a cache hit bandwidth from monitoring performance of the cache;

calculating an active cache leakage power in dependence on a proportion of the cache which is currently powered;

calculating a memory bandwidth equivalent for expending the active cache leakage power on memory access; and

when the cache hit bandwidth is less than the memory bandwidth equivalent, reducing the proportion of the cache which is currently powered.

2. The method as claimed in claim 1 , wherein the cache comprises multiple banks, wherein at least one bank of the multiple banks is capable of being powered off independently of a remainder of the multiple banks.

3. The method as claimed in claim 2 , wherein each bank of the multiple banks is capable of being individually powered off.

4. The method as claimed in claim 2 , wherein reducing the proportion of the cache which is currently powered comprises powering off at least one bank of the multiple banks.

5. The method as claimed in claim 2 , wherein the proportion of the cache which is currently powered is given by a number of the multiple banks which are currently powered.

6. The method as claimed in claim 1 , wherein the active cache leakage power is calculated in dependence on a power-down threshold factor, wherein the power-down threshold factor reduces a value of the proportion of the cache which is currently powered when the value is used in calculating the active cache leakage power.

7. The method as claimed in claim 6 , wherein the power-down threshold factor can be set in a range such that the value of the proportion of the cache which is currently powered used in calculating the active cache leakage power ranges between:

the proportion of the cache which is currently powered for a first power-down threshold factor value; and

the proportion of the cache which is currently powered less an increment proportion of the cache which is capable of being powered down for a second power-down threshold factor value.

8. The method as claimed in claim 7 , wherein the power-down threshold factor is set to a value nearer to the second power-down threshold factor value than the first power-down threshold factor value.

9. The method as claimed in claim 1 , comprising the further steps, taken when the proportion of the cache which is currently powered is less than all of the cache, of:

calculating a cache miss bandwidth from monitoring performance of the cache;

calculating an increment cache leakage power in dependence on an increment proportion of the cache which is currently not powered;

calculating a cache hit bandwidth equivalent for incurring the increment cache leakage power; and

when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, increasing the proportion of the cache which is currently powered by the increment proportion.

10. The method as claimed in claim 9 , wherein the cache comprises multiple banks, wherein at least one bank of the multiple banks is capable of being powered off independently of a remainder of the multiple banks, wherein the increment proportion of the cache is a bank of the multiple banks.

11. The method as claimed in claim 9 , wherein the increment cache leakage power is calculated in dependence on a power-up threshold factor, wherein the power-up threshold factor reduces a value of the increment proportion of the cache which is currently not powered when the value is used in calculating the increment cache leakage power.

12. The method as claimed in claim 11 , wherein the power-up threshold factor can be set in a range such that the value of the increment proportion of the cache which is currently not powered used in calculating the increment cache leakage power ranges between:

the increment proportion of the cache which is currently not powered for a first power-up threshold factor value; and

zero for a second power-up threshold factor value.

13. The method as claimed in claim 12 , wherein the power-up threshold factor is set to a value nearer to the first power-up threshold factor value than the second power-up threshold factor value.

14. The method as claimed in claim 1 , comprising the further steps, after reducing the proportion of the cache which is currently powered, of:

monitoring a cache miss rate; and

when the cache miss rate exceeds a predetermined cache miss rate threshold for a predetermined period, increasing the proportion of the cache which is currently powered.

15. The method as claimed in claim 14 , comprising at least one of the further steps of:

delaying a calculation of whether the memory bandwidth equivalent exceeds the cache hit bandwidth; and

delaying any subsequent reduction in the proportion of the cache which is currently powered.

16. The method as claimed in claim 1 , wherein monitoring performance of the cache comprises monitoring a global cache performance.

17. The method as claimed in claim 2 , wherein monitoring performance of the cache comprises monitoring per-bank cache performances.

18. A computing device readable storage medium in which instructions are stored in a non-transient fashion which when executed by a computing device cause the computing device to carry out the method of claim 1 .

19. Apparatus for operating a cache comprising:

cache monitoring circuitry to monitor performance of the cache;

cache performance calculation circuitry to receive performance data from the cache monitoring circuitry and to:

calculate a cache hit bandwidth from the performance data,

calculate an active cache leakage power in dependence on a proportion of the cache which is currently powered, and

calculate a memory bandwidth equivalent for expending the active cache leakage power on memory access; and

cache power control circuitry to reduce the proportion of the cache which is currently powered when the cache hit bandwidth is less than the memory bandwidth equivalent.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2017
From: CRAWFORD, ASHLEY JOHN; ROSE, ANDREW CHRISTOPHER; THOMAS, TESSIL; FANDOS, DAVID GUILLEN
To: ARM LIMITED
Reel/Frame 042496/0027 →
Priority Claims (1)
GB 1603741.8 · Mar 4, 2016 · national
Continuity (1)
Related Publication 20170255248A1 · Sep 7, 2017
Cited By (2)
US 12,379,857 US 12,598,647