Asymmetric power states on a communication link
Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.
1. A peer-to-peer Peripheral Component Interconnect (PCI) express (PCIe) system, comprising:
a PCIe bus;
a first link terminus comprising:
a first physical layer (PHY) coupled to the PCIe bus;
a second link terminus comprising:
a second PHY coupled to the PCIe bus;
a reference clock configured to provide a reference clock signal to the first link terminus and to the second link terminus; and
a first switch associated with the reference clock configured to stop sending the reference clock signal to one of the first link terminus and the second link terminus while maintaining provision of the reference clock signal to the other one of the first link terminus and the second link terminus.
2. The peer-to-peer PCIe system of claim 1 , wherein the first link terminus is a PCIe endpoint.
3. The peer-to-peer PCIe system of claim 1 , wherein the second link terminus is a PCIe root complex.
4. The peer-to-peer PCIe system of claim 1 , further comprising a second switch associated with the reference clock configured to stop sending the reference clock signal to the other one of the first link terminus and the second link terminus while maintaining provision of the reference clock signal to the one of the first link terminus and the second link terminus.
5. The peer-to-peer PCIe system of claim 3 , wherein the second link terminus comprises the reference clock.
6. The peer-to-peer PCIe system of claim 1 , wherein the reference clock is distinct from the first link terminus and the second link terminus.
7. The peer-to-peer PCIe system of claim 1 , wherein the first link terminus and the second link terminus are configured to vote on entry into a low-power state and provision of the reference clock signal is based on the vote.
8. The peer-to-peer PCIe system of claim 1 , wherein the reference clock signal is provided to the second link terminus over the PCIe bus.
9. The peer-to-peer PCIe system of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.