High performance interconnect link layer
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
1. An apparatus comprising:
a host processor comprising:
physical layer logic; and
link layer logic, comprising circuitry to:
generate a flit comprising a plurality of slots, wherein one or more of the slots is encoded with a return credit response, at least one other one of the plurality of slots is encoded as a null slot, the flit is according to a format to enable a plurality of transaction headers to be contained in the flit, and the flit comprises a piece of a larger network packet; and
a transmitter to send the flit on a link to another device.
2. The apparatus of claim 1 , wherein a single one of the slots is encoded with the return credit response.
3. The apparatus of claim 1 , wherein the other device comprises another host processor device.
4. The apparatus of claim 1 , wherein the link supports a plurality of lane widths.
5. The apparatus of claim 4 , wherein the plurality of lane widths comprises a lane width of at least 8 lanes.
6. The apparatus of claim 1 , wherein the flit comprises at least 192 bits.
7. The apparatus of claim 1 , wherein the physical layer comprises an electrical transmission medium.
8. The apparatus of claim 1 , wherein the physical layer comprises an optical transmission medium.
9. An apparatus comprising:
a host processor comprising:
a receiver to receive a flit from another device over a link, wherein the flit comprises a plurality of slots, one or more of the slots is encoded with a return credit response, at least one other one of the plurality of slots is encoded as a null slot, the flit is according to a format to enable a plurality of transaction headers to be contained in the flit, and the flit comprises a piece of a larger network packet;
a protocol stack comprising physical layer logic and link layer logic, wherein the link layer logic is to return a number of credits to a credit pool based on the return credit response.
10. The apparatus of claim 9 , wherein the credit pool corresponds to a virtual channel of the link.
11. The apparatus of claim 9 , wherein a single one of the slots is encoded with the return credit response.
12. The apparatus of claim 9 , wherein the other device comprises another host processor device.
13. The apparatus of claim 9 , wherein the link supports a plurality of lane widths.
14. The apparatus of claim 13 , wherein the plurality of lane widths comprises a lane width of at least 8 lanes.
15. The apparatus of claim 9 , wherein the flit comprises at least 192 bits.
16. The apparatus of claim 9 , wherein the physical layer comprises an electrical transmission medium.
17. The apparatus of claim 9 , wherein the physical layer comprises an optical transmission medium.
18. A system comprising:
a first host processor device;
a second host processor device to connect to the first host processor device using a link, wherein the second host processor device comprises:
physical layer logic; and
link layer logic, wherein the link layer logic is to:
generate a flit comprising a plurality of slots, wherein a particular one of the plurality of slots is encoded with a return credit response, another one of the slots in the plurality of slots is encoded as a null slot, the flit is according to a format to enable a plurality of transaction headers to be contained in the flit, and the flit comprises a piece of a larger network packet; and
a transmitter to send the flit on a link to another device.
19. The system of claim 18 , wherein a single one of the slots is encoded with the return credit response.
20. The system of claim 18 , wherein the other device comprises another host processor device.
21. The system of claim 18 , wherein the link supports a plurality of lane widths.
22. The system of claim 21 , wherein the plurality of lane widths comprises a lane width of at least 8 lanes.
23. The system of claim 18 , wherein the flit comprises at least 192 bits.
24. The system of claim 18 , wherein the physical layer comprises an electrical transmission medium.
25. The system of claim 18 , wherein the physical layer comprises an optical transmission medium.
26. A system comprising:
means for generating a flit comprising a plurality of slots, wherein one or more of the slots is encoded with a return credit response, at least one other one of the plurality of slots is encoded as a null slot, the flit is according to a format to enable a plurality of transaction headers to be contained in the flit, and the flit comprises a piece of a larger network packet; and
means for sending the flit on a link to another device.