Adjustment circuit for partitioned memory block
View Patent ↗The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.
1. An adjustment circuit comprising:
a controller circuit configured to output a control signal that indicates a memory type;
a timer circuit configured to output a timing signal for a read memory operation based on the control signal;
a temperature adaptive reference (TAR) generator configured to adjust a verify reference current for a verify memory operation based on temperature, wherein the verify reference current is set based on the control signal; and
an amplifier circuit configured to:
receive the timing signal, the verify current, and a current provided by a memory cell, wherein the amplifier circuit outputs a signal based on the timing signal, the verify current, and the memory cell current.
2. The adjustment circuit of claim 1 , wherein the timing signal comprises a first timer value for a first memory type or a second timer value for a second memory type.
3. The adjustment circuit of claim 2 , wherein the first memory type comprises code memory and the second memory type comprises data memory.
4. The adjustment circuit of claim 3 , wherein memory space allocated to the data memory is dynamically adjustable.
5. The adjustment circuit of claim 1 , wherein the TAR generator comprises:
a bandgap reference current generator configured to output a proportional to absolute temperature (PTAT) current;
a first current mirror circuit configured to multiply the PTAT current to generate a modified PTAT current; and
a second current mirror circuit configured to multiply the modified PTAT current by a factor to generate the verify reference current, wherein the factor is determined based on the control signal.
6. The adjustment circuit of claim 5 , wherein the second current mirror circuit is further configured to multiply a current provided by one or more reference cells to generate the verify reference current.
7. The adjustment circuit of claim 6 , wherein the first memory type comprises code memory and the second memory type comprises data memory, and wherein memory space allocated to the data memory is dynamically adjustable.
8. The adjustment circuit of claim 5 , wherein the TAR generator further comprises a third current mirror circuit configured to couple the verify reference current from the second current mirror circuit to the amplifier circuit.
9. A memory system, comprising:
a memory array divided into a plurality of memory blocks, wherein one or more of the plurality of memory blocks is partitioned into memory sectors associated with respective memory types; and
an adjustment circuit comprising:
a controller circuit configured to output a control signal that indicates a memory type;
a timer circuit configured to output a timing signal to the plurality of memory blocks for a read memory operation based on the control signal;
a temperature adaptive reference (TAR) generator configured to adjust a verify reference current for a verify memory operation based on temperature, wherein the verify reference current is set based on the control signal; and
an amplifier circuit configured to:
receive the timing signal, the verified current, and a current provided by a memory cell of the plurality of memory blocks; and
compare the verify current and the current provided by the memory cell for a duration based on the timing signal.
10. The memory system of claim 9 , wherein the timing signal comprises a first timer value for a first memory type or a second timer value for a second memory type.
11. The memory system of claim 10 , wherein the first memory type comprises code memory and the second memory type comprises data memory.
12. The memory system of claim 11 , wherein memory space allocated to the data memory is dynamically adjustable.
13. The memory system of claim 9 , wherein the TAR generator comprises:
a bandgap reference current generator configured to output a proportional to absolute temperature (PTAT) current;
a first current mirror circuit configured to multiply the PTAT current to generate a modified PTAT current;
a second current mirror circuit configured to generate the adjusted verify reference current based on the modified PTAT current, wherein the second current mirror circuit comprises a plurality of selectable transistors selected based on the control signal.
14. The memory system of claim 13 , wherein the plurality of selectable transistors are selected based on a first memory type or a second memory type.
15. The memory system of claim 14 , wherein the first memory type comprises code memory and the second memory type comprises data memory.
16. The memory system of claim 15 , wherein memory space allocated to the data memory is dynamically adjustable.
17. A method for memory operations, comprising:
determining whether a control signal indicates a first memory type or a second memory type;
in response to the determining the control signal indicates the first memory type:
activating a sense amplifier for a first duration for a read memory operation;
adjusting a verify reference current based on temperature, wherein the verify reference current is set based on the first memory type; and
outputting the adjusted verify reference current to the sense amplifier for a verify memory operation; and
in response to the determining the control signal indicates the second memory type:
activating a sense amplifier for a second duration for the read memory operation;
adjusting the verify reference current based on temperature, wherein the verify reference current is set based on the second memory type; and
outputting the adjusted verify reference current to the sense amplifier for the verify memory operation.
18. The method of claim 17 , wherein the first memory type comprises code memory and the second memory type comprises data memory, and wherein the first timer value is less than the second timer value.
19. The method of claim 17 , wherein adjusting the verify reference current based on current comprises:
outputting a proportional to absolute temperature (PTAT) current;
outputting a reference cell current;
multiplying the PTAT current and the reference cell current to generate a modified PTAT current; and
generating the adjusted verify reference current based on the modified PTAT current.
20. The method of claim 19 , wherein generating the adjusted verify reference current comprises selecting one or more transistors based on the control signal.