Structure with embedded memory device and contact isolation scheme
The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.
1. A method of fabricating an integrated circuit, comprising:
forming a source and a drain on a fin active region of a semiconductor substrate;
depositing an interlayer dielectric (ILD) layer on the source and drain;
patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively;
forming a dielectric material layer in the first contact hole;
forming a dielectric feature in the first contact hole, wherein the dielectric feature has a bottom surface directly contacting the source and sidewalls directly contacting the dielectric material layer; and
forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively, wherein the forming of the dielectric material layer in the first contact hole includes
depositing the dielectric material layer in the first contact hole; and
performing an anisotropic etching process to remove a bottom portion of the dielectric material layer within the first contact hole such that the source is exposed.
2. The method of claim 1 , wherein the first conductive feature is separated from the source by the dielectric material layer.
3. The method of claim 2 , wherein
the forming of the dielectric material layer includes depositing the dielectric material layer directly on the source within the first contact hole; and
the forming of the first and second conductive features includes forming the first conductive feature directly on the dielectric material layer within the first contact hole.
4. The method of claim 3 , wherein the forming of the first and second conductive features includes
depositing a glue layer in the first and second contact holes;
filling a conductive material on the glue layer within the first and second contact holes; and
performing a chemical mechanical polishing to remove excessive of the conductive material on the ILD layer.
5. The method of claim 4 , further comprising forming a gate stack on the fin active region and being interposed between the source and drain, wherein the gate stack, the source and the drain are configured to a field-effect transistor.
6. The method of claim 5 , wherein the dielectric material layer includes one of silicon oxide, silicon nitride and silicon oxynitride.
7. The method of claim 6 , wherein
the glue layer includes a titanium film and a titanium nitride film; and
the conductive material includes one of tungsten, copper, aluminum, and a combination thereof.
8. The method of claim 5 , further comprising forming a dielectric capping layer on the gate stack and the ILD layer before the depositing of the ILD layer on the source and drain.
9. The method of claim 1 , wherein the forming of the dielectric feature in the first contact hole includes performing a bottom-up deposition, wherein dielectric feature includes a dielectric material different from that of the dielectric material layer.
10. The method of claim 1 , further comprising forming a gate stack on the fin active region, wherein the gate stack includes a metal electrode;
depositing a silicon layer on the metal electrode;
annealing to react the silicon layer and a metal of the metal electrode, thereby forming a silicide layer on the metal electrode; and
etching to remove unreacted silicon.
11. A method, comprising:
forming a metal gate stack on a fin active region of a semiconductor substrate;
forming a source and a drain on the fin active region, the source and drain being doped with a same type of dopant;
forming a silicide layer self-aligned on the metal gate stack;
forming an interlayer dielectric (ILD) layer on the source and the drain;
patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively;
forming a dielectric material layer in the first contact hole; and
forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively, wherein the first conductive feature is separated from the source by the dielectric material layer and the second conductive feature directly contacts the drain.
12. The method of claim 11 , wherein
the forming of the dielectric material layer in the first contact hole includes depositing the dielectric material layer directly on the source within the first contact hole;
the forming of the first and second conductive features includes forming the first conductive feature on the dielectric material layer within the first contact hole; and
the first conductive feature is separated from the source by the dielectric material layer.
13. The method of claim 11 , wherein the forming of the dielectric material layer in the first contact hole includes
depositing the dielectric material layer in the first and second contact hole; and
removing portions of the dielectric material layers from bottom surfaces of the first and second contact holes.
14. The method of claim 13 , further comprising forming a resistive material layer in the first contact hole, wherein
the resistive material layer is a dielectric material different from the dielectric material layer in composition;
the resistive material layer is surrounded by the dielectric material layer and is directly landing on the source; and
the first conductive feature is directly landing on the resistive material layer.
15. The method of claim 13 , further comprising:
forming a patterned mask layer on the dielectric material layer to cover the first contact hole; and
performing an etching process to remove a bottom portion of the dielectric material layer in the second contact hole.
16. The method of claim 11 , wherein the forming of the first and second conductive features includes
depositing a glue layer in the first and second contact holes;
filling a conductive material on the glue layer within the first and second contact holes; and
performing a chemical mechanical polishing to remove excessive portions of the conductive material on the ILD layer.
17. The method of claim 11 , wherein the forming of the silicide layer self-aligned on the metal gate stack includes
depositing a silicon layer on the metal gate stack;
annealing to react the silicon layer and the metal gate stack, thereby forming a silicide layer on the metal gate stack; and
etching to remove unreacted silicon.
18. A method of fabricating an integrated circuit, comprising:
forming a source and a drain on a fin active region of a semiconductor substrate;
depositing an interlayer dielectric (ILD) layer on the source and drain;
patterning the ILD layer to form a through hole to expose the drain;
patterning the ILD to form a recess hole vertically aligning with the source and with a bottom portion of the ILD remained within the recess hole; and
depositing to form a first conductive feature in the recess hole and a second conductive feature in the through hole,
wherein the first conductive feature is separated from the source by the bottom portion of the ILD and the second conductive feature directly contacts the drain.
19. The method of claim 18 , further comprising forming a gate stack on a semiconductor substrate, wherein the gate stack spans from the source to the drain, and wherein the source, drain and gate stack constitute portions of a field-effect transistor.
20. The method of claim 18 , wherein the forming of the source and drain includes forming the source and drain both being doped with a same type of dopant.