Memory system that carries out temperature-based access to a memory chip
A memory system is connectable to a host and comprises a memory chip including a nonvolatile semiconductor memory cell array, a memory controller, a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller, and a second temperature sensor positioned to measure a second temperature, which is representative of a temperature of the memory chip. The memory controller is configured to compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature and carry out access to the memory chip when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature.
1. A memory system connectable to a host, comprising:
a memory chip including a nonvolatile semiconductor memory cell array;
a memory controller including an error correcting code (ECC) circuit;
a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller; and
a second temperature sensor positioned to measure a second temperature, which is representative of a temperature of the memory chip, wherein
the memory controller is configured to, prior to performing a read access to the memory chip:
compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature,
carry out the read access to the memory chip when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature, and
block the read access to the memory chip and operate the ECC circuit using dummy data, when neither the first temperature is greater than the first threshold temperature nor the second temperature is greater than the second threshold temperature.
2. The memory system according to claim 1 , wherein
the ECC circuit includes an encoding circuit, and the memory controller causes the encoding circuit to encode the dummy data.
3. The memory system according to claim 1 , wherein
the ECC circuit includes a decoding circuit, and the memory controller causes the decoding circuit to decode the dummy data.
4. The memory system according to claim 1 , wherein
the read access is included in an operation of copying data from a block of the nonvolatile semiconductor memory cell array to another block of the semiconductor memory cell array.
5. The memory system according to claim 1 , wherein
the memory controller is configured to carry out an initial read access of the memory chip without regard to the first and second temperatures in response to a read command received from the host, and then compares the first temperature against the first threshold temperature and the second temperature against the second threshold temperature when the initial read access fails.
6. A memory system connectable to a host, comprising:
a plurality of memory chips, each of which includes a nonvolatile semiconductor memory cell array;
a memory controller;
a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller; and
a plurality of second temperature sensors, each of which is positioned to measure a second temperature representative of a temperature of one of the memory chips, wherein
the memory controller is configured to, prior to performing a read access to the memory chips, compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature, and perform a heating operation while preventing the read access to the memory chips when neither the first temperature is greater than the first threshold temperature nor at least one of the second temperatures is greater than the second threshold temperature.
7. The memory system according to claim 6 , wherein
the memory controller includes an error correcting code (ECC) circuit, and operates the ECC circuit to perform the heating operation.
8. The memory system according to claim 6 , wherein
the memory controller is configured to select one of the memory chips having a temperature higher than the second threshold temperature, as a target memory chip to be accessed.
9. The memory system according to claim 6 , wherein
the memory controller is configured to determine a target memory chip to be accessed based on a write command received from the host, and change the target memory chip if the temperature corresponding to the target memory chip is lower than the second threshold temperature and if one of the other memory chips has a temperature that is higher than the second threshold temperature.
10. A method for operating a memory system including a memory chip having a nonvolatile semiconductor memory cell array, and a memory controller, the method comprising:
detecting a first temperature of the memory controller;
detecting a second temperature of the memory chip;
comparing the first temperature of the memory controller against a first threshold temperature;
comparing the second temperature of the memory chip against a second threshold temperature;
accessing the memory chip to carry out an operation in response to a read command from a host, when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature; and
performing a heating operation in response to the read command from the host while preventing a read access to the memory chip, when neither the first temperature is greater than the first threshold temperature nor the second temperature is greater than the second threshold temperature.
11. The method according to claim 10 , wherein
the memory controller includes an error correcting code (ECC) circuit, and
the heating operation includes operating the ECC circuit.
12. The method according to claim 10 , further comprising:
accessing the memory chip without regard to the first and second temperatures in response to an earlier command received from the host prior to the read command; and
only after detecting that access to the memory chip in response to the earlier command failed, performing the conditional read access to the memory chip based on the detected first and second temperatures, and the first and second threshold temperatures.
13. The memory system according to claim 3 , wherein
after the decoding circuit has decoded the dummy data, the memory controller reads data from the memory chip and control the decoding circuit to decode the read data when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature.
14. The memory system according to claim 13 , wherein
the read of the data is triggered by a read command from the host that designates a logical address of the data, and
the memory controller determines a physical address in the memory chip, mapped to the logical address.