IP Library › Granted Patent US 10,373,895

Granted Patent B2

US 10,373,895 · App. 15/375,812 · Granted Aug 6, 2019

Semiconductor device having die pads with exposed surfaces

Inventors: Edward Fuergut (Dasing, DE); Martin Gruber (Schwandorf, DE); Wolfgang Scholz (Olching, DE); Ralf Otremba (Kaufbeuren, DE)

Assignee: Infineon Technologies Austria AG

H01L23/49537 H01L21/4825 H01L21/4842 H01L21/4882 H01L21/52 H01L21/56 H01L23/3114 H01L23/4952 H01L23/49562 H01L23/49575 H01L25/0652 H01L21/561 H01L23/3107 H01L2224/0603 H01L2224/48472 H01L2224/4903 H01L2224/49111 H01L2224/97 H01L2225/0651 H01L2225/06506 H01L2225/06544 H01L2225/06555 H01L2225/06589

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 10,373,895
App. No.: 15/375,812
Granted: Aug 6, 2019
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame includes a first die pad having a first surface and a second surface opposite to the first surface. The second lead frame includes a second die pad having a first surface and a second surface opposite to the first surface. The first surface of the second die pad faces the first surface of the first die pad. The first semiconductor chip is attached to the first surface of the first die pad. The encapsulation material encapsulates the first semiconductor chip and portions of the first lead frame and the second lead frame. The encapsulation material has a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

Claims (61)

1. A semiconductor device comprising:

a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad;

a second lead frame comprising a second die pad having a first surface and a second surface opposite to the first surface of the second die pad, the first surface of the second die pad facing the first surface of the first die pad, wherein the second die pad is directly electrically connected to the first die pad;

a first semiconductor chip attached to the first surface of the first die pad; and

2. The semiconductor device of claim 1 , further comprising:

a second semiconductor chip attached to the first surface of the second die pad.

3. The semiconductor device of claim 2 , wherein the first semiconductor chip is electrically coupled to the second semiconductor chip.

4. The semiconductor device of claim 1 , further comprising:

bond wires electrically coupling the first semiconductor chip to leads of the first lead frame.

5. A semiconductor device comprising:

a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad;

a first semiconductor chip attached to the first surface of the first die pad; and

an encapsulation material encapsulating the first semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad, a hole through the encapsulation material extending from the first surface of the encapsulation material to the second surface of the encapsulation material.

6. A semiconductor device comprising:

a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad;

a first semiconductor chip attached to the first surface of the first die pad; and

an encapsulation material encapsulating the first semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad, wherein the semiconductor device is a through-hole device.

7. The semiconductor device of claim 1 , wherein the semiconductor device is a surface mount device.

8. A semiconductor device comprising:

a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad;

a first semiconductor chip attached to the first surface of the first die pad;

a second semiconductor chip attached to the first surface of the second die pad; and

an encapsulation material encapsulating the first semiconductor chip and the second semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

9. The semiconductor device of claim 8 , further comprising:

a third semiconductor chip; and

a fourth semiconductor chip;

wherein the first lead frame comprises a third die pad having a first surface and a second surface opposite to the first surface of the third die pad;

wherein the second lead frame comprises a fourth die pad having a first surface and a second surface opposite to the first surface of the fourth die pad;

wherein the third semiconductor chip is attached to the first surface of the third die pad;

wherein the fourth semiconductor chip is attached to the first surface of the fourth die pad; and

wherein the encapsulation material encapsulates the third semiconductor chip and the fourth semiconductor chip and wherein the first surface of the encapsulation material is aligned with the second surface of the third die pad and the second surface of the encapsulation material is aligned with the second surface of the fourth die pad.

10. The semiconductor device of claim 8 , wherein the first semiconductor chip comprises a power semiconductor chip; and

wherein the second semiconductor chip comprises a logic chip.

11. The semiconductor device of claim 8 , wherein the first semiconductor chip comprises a power transistor chip; and

wherein the second semiconductor chip comprises a diode chip.

12. The semiconductor device of claim 8 , wherein the first semiconductor chip comprises a first power transistor chip; and

wherein the second semiconductor chip comprises a second power transistor chip.

13. The semiconductor device of claim 8 , further comprising:

an interconnect board between the first semiconductor chip and the second semiconductor chip electrically coupling the first semiconductor chip to the second semiconductor chip.

14. A method to fabricate a semiconductor device, the method comprising:

attaching a first semiconductor chip to a first surface of a first die pad of a first lead frame, the first die pad having a second surface opposite to the first surface of the first die pad;

attaching a second semiconductor chip to a first surface of a second die pad of a second lead frame, the second die pad having a second surface opposite to the first surface of the second die pad;

stacking the second lead frame on the first lead frame such that the first surface of the first die pad faces the first surface of the second die pad; and

encapsulating the first semiconductor chip and the second semiconductor chip and portions of the first lead frame and the second lead frame with an encapsulation material such that the second surface of the first die pad is aligned with a first surface of the encapsulation material and the second surface of the second die pad is aligned with a second surface of the encapsulation material.

15. The method of claim 14 , further comprising:

electrically coupling the second lead frame to the first lead frame.

16. The method of claim 14 , further comprising:

cutting leads of the second lead frame after stacking the second lead frame on the first lead frame.

17. The method of claim 14 , further comprising:

wire bonding the first semiconductor chip to leads of the first lead frame; and

wire bonding the second semiconductor chip to leads of the second lead frame.

18. The method of claim 14 , further comprising:

electrically coupling the first semiconductor chip to the second semiconductor chip.

19. The method of claim 14 , further comprising:

attaching a first heat sink to the second surface of the first die pad and the first surface of the encapsulation material; and

attaching a second heat sink to the second surface of the second die pad and the second surface of the encapsulation material.

20. The semiconductor device of claim 1 , the first lead frame including a first lead extending directly from the first die pad, and the second lead frame being directly electrically connected to the first die pad by a lead portion extending from the second die pad and directly connecting to the first lead.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2016

From: FUERGUT, EDWARD; GRUBER, MARTIN; SCHOLZ, WOLFGANG; OTREMBA, RALF

To: INFINEON TECHNOLOGIES AUSTRIA AG

Reel/Frame 040709/0909 →

Continuity (1)

Related Publication 20180166366A1 · Jun 14, 2018