Array substrate, display panel and display device
View Patent ↗An array substrate, a display panel and a display device, including at least two gate lines in a display area, a gate driving circuit and at least two gate fan-out lines in a non-display are described. One end of each of the gate fan-out lines are electrically connected with one signal output of the gate driving circuit and the other end of each of the gate fan-out lines are electrically connected with the gate lines. By configuring a first gate fan-out line of the gate fan-out lines and the gate driving circuit to have an overlapping area outside a mutual connection area, an area where the gate fan-out lines are overlaps the gate driving circuit, space occupied by the first gate fan-out line outside the gate driving circuit is decreased to shorten a distance between the gate driving circuit and the display area.
1. An array substrate, comprising:
a display area, a non-display area surrounding the display area, at least two gate lines in the display area, a gate driving circuit and at least two gate fan-out lines in the non-display area, respectively, wherein:
one end of each of the gate fan-out lines is electrically connected with one of at least two signal outputs of the gate driving circuit and the other end of each of the gate fan-out lines is electrically connected with one of the gate lines; and
a first gate fan-out line of the gate fan-out lines overlaps the gate driving circuit in an overlapping area outside a mutual electrical connection area, and a portion of the first gate fan-out line in the overlapping area and the gate driving circuit are arranged in different layers;
in an extension direction of the gate lines, a distance between the signal output electrically connected with the first gate fan-out line and an edge of the gate driving circuit closest to the display area is a first distance, a distance between the signal output electrically connected with the first gate fan-out line and an edge of the gate driving circuit farthest away from the display area is a second distance, and the first distance is greater than or equal to the second distance.
2. The array substrate according to claim 1 , wherein:
the gate fan-out lines are first gate fan-out lines.
3. The array substrate according to claim 1 , wherein:
the signal output electrically connected with the first gate fan-out line is at an edge of the gate driving circuit position farthest away from the display area.
4. The array substrate according to claim 1 , wherein:
a distance between the gate driving circuit and the display area is greater than or equal to 40 μm and is smaller than 100 μm.
5. The array substrate according to claim 1 , wherein:
the array substrate further comprises at least two touch signal lines in the display area; and
the portion of the first gate fan-out line inside the overlapping area and the touch signal lines are arranged in the same layer.
6. The array substrate according to claim 5 , wherein:
the array substrate further comprises an underlying substrate, a first organic insulated layer and a first inorganic insulated layer;
the first gate fan-out line is located on one side of the gate driving circuit farthest away from the underlying substrate, the first organic insulated layer and the first inorganic insulated layer are located between the first gate fan-out line and the gate driving circuit, and the first organic insulated layer is located on one side of the first inorganic insulated layer farthest away from the underlying substrate; and
the first gate fan-out line is electrically connected with the corresponding signal output through a via hole.
7. The array substrate according to claim 5 , wherein:
the array substrate further comprises at least two data lines in the display area, the data lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect;
the gate lines extend along the second direction and are arranged along the first direction, and the gate lines and the data lines intersect to define at least two pixels; and
the data lines and the touch signal lines are arranged in different layers, and a touch signal line and a data line overlap in a direction perpendicular to a plane where the array substrate is located.
8. The array substrate according to claim 1 , wherein:
the portion of the first gate fan-out line outside the overlapping area and a portion of the first gate fan-out line inside the overlapping area are arranged in different layers.
9. The array substrate according claims 1 , wherein:
all corners of the array substrates are right angles; or
the array substrate at least comprises one non-right-angle corner.
10. The array substrate according to claim 9 , wherein:
all the corners of the array substrate are right angles; and
the gate lines are arranged in a first direction, and the length of the gate driving circuit in the first direction is shorter than the length of the display area in the first direction.
11. An array substrate, comprising:
a display area, a non-display area surrounding the display area, at least two gate lines in the display area, a gate driving circuit and at least two gate fan-out lines in the non-display area, respectively, wherein:
one end of each of the gate fan-out lines is electrically connected with one of at least two signal outputs of the gate driving circuit and the other end of each of the gate fan-out lines is electrically connected with one of the gate lines; and
a first gate fan-out line of the gate fan-out lines overlaps the gate driving circuit in an overlapping area outside a mutual electrical connection area, and a portion of the first gate fan-out line in the overlapping area and the gate driving circuit are arranged in different layers;
wherein the array substrate further comprises at least two touch signal lines in the display area; and
the portion of the first gate fan-out line inside the overlapping area and the touch signal lines are arranged in the same layer;
wherein the array substrate further comprises an underlying substrate, a first organic insulated layer and a first inorganic insulated layer;
the first gate fan-out line is located on one side of the gate driving circuit farthest away from the underlying substrate, the first organic insulated layer and the first inorganic insulated layer are located between the first gate fan-out line and the gate driving circuit, and the first organic insulated layer is located on one side of the first inorganic insulated layer farthest away from the underlying substrate; and
the first gate fan-out line is electrically connected with the corresponding signal output through a via hole.
12. The array substrate according to claim 11 , wherein:
the gate fan-out lines are first gate fan-out lines.
13. The array substrate according to claim 11 , wherein:
a distance between the gate driving circuit and the display area is greater than or equal to 40 μm and is smaller than 100 μm.
14. The array substrate according to claim 11 , wherein:
the array substrate further comprises at least two data lines in the display area, the data lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect;
the gate lines extend along the second direction and are arranged along the first direction, and the gate lines and the data lines intersect to define at least two pixels; and
the data lines and the touch signal lines are arranged in different layers, and a touch signal line and a data line overlap in a direction perpendicular to a plane where the array substrate is located.
15. The array substrate according to claim 11 , wherein:
the portion of the first gate fan-out line outside the overlapping area and a portion of the first gate fan-out line inside the overlapping area are arranged in different layers.
16. An array substrate, comprising:
a display area, a non-display area surrounding the display area, at least two gate lines in the display area, a gate driving circuit and at least two gate fan-out lines in the non-display area, respectively, wherein:
one end of each of the gate fan-out lines is electrically connected with one of at least two signal outputs of the gate driving circuit and the other end of each of the gate fan-out lines is electrically connected with one of the gate lines; and
a first gate fan-out line of the gate fan-out lines overlaps the gate driving circuit in an overlapping area outside a mutual electrical connection area, and a portion of the first gate fan-out line in the overlapping area and the gate driving circuit are arranged in different layers;
wherein:
the portion of the first gate fan-out line outside the overlapping area and a portion of the first gate fan-out line inside the overlapping area are arranged in different layers.
17. The array substrate according to claim 16 , wherein:
the gate fan-out lines are first gate fan-out lines.
18. The array substrate according to claim 16 , wherein:
a distance between the gate driving circuit and the display area is greater than or equal to 40 μm and is smaller than 100 μm.
19. The array substrate according to claim 16 , wherein:
the array substrate further comprises at least two touch signal lines in the display area; and
the portion of the first gate fan-out line inside the overlapping area and the touch signal lines are arranged in the same layer.
20. The array substrate according to claim 19 , wherein:
the array substrate further comprises at least two data lines in the display area, the data lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect;
the gate lines extend along the second direction and are arranged along the first direction, and the gate lines and the data lines intersect to define at least two pixels; and
the data lines and the touch signal lines are arranged in different layers, and a touch signal line and a data line overlap in a direction perpendicular to a plane where the array substrate is located.