Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays
A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.
1. A method for integrating an electronic component in back end of the line (BEOL) processing, the method comprising:
forming a first electrode over a semiconductor substrate;
forming a first electrically conductive material over a portion of the first electrode;
forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction;
depositing a second electrode between a set of spacers and in direct contact with the p-n-junction;
depositing a phase change material over the p-n junction and in direct contact with the second electrode; and
forming a third electrode over a portion of the phase change material.
2. The method of claim 1 , wherein the first electrically conductive material is an n-type poly-silicon layer.
3. The method of claim 2 , wherein second electrically conductive material is a p-type poly-silicon layer.
4. The method of claim 1 , further comprising forming the p-n junction and the second electrode between interlayer dielectric (ILD) regions.
5. The method of claim 1 , wherein the phase change material extends a length of the first electrode.
6. The method of claim 1 , wherein the electronic component is a poly-silicon diode.
7. The method of claim 1 , wherein the p-n junction is an access device and the phase change material is a memory element, the access device combined with the memory element to be positioned between a plurality of first and third electrodes defining a crosspoint array.
8. A method for integrating an electronic component in back end of the line (BEOL) processing, the method comprising:
forming a first electrode over a semiconductor substrate;
forming a first electrically conductive material over the first electrode;
forming an undoped intrinsic semiconductor layer over the first electrically conductive material;
forming a second electrically conductive material over the undoped intrinsic semiconductor layer, where the first electrically conductive material, the undoped intrinsic semiconductor layer, and the second electrically conductive material define a p-i-n junction;
depositing a second electrode between a set of spacers and in direct contact with the p-i-n-junction;
depositing a phase change material over t p-i-n junction and in direct contact with the second electrode; and
forming a third electrode over a portion of the phase change material.
9. The method of claim 8 , wherein the first electrically conductive material is an n-type poly-silicon layer.
10. The method of claim 9 , wherein second electrically conductive material is a p-type poly-silicon layer.
11. The method of claim 8 , further comprising forming the p-i-n junction and the second electrode between interlayer dielectric (ILD) regions.
12. The method of claim 8 , wherein the phase change material extends a length of the first electrode and a length of the first electrically conductive material.
13. The method of claim 8 , wherein the electronic component is a poly-silicon diode.
14. The method of claim 8 , wherein the p-i-n junction is an access device and the phase change material is a memory element, the access device combined with the memory element to be positioned between a plurality of first and third electrodes defining a crosspoint array.
15. A semiconductor structure for integrating an electronic component in back end of the line (BEOL) processing, the structure comprising:
a first electrode disposed over a semiconductor substrate;
a first electrically conductive material disposed over a portion of the first electrode;
a second electrically conductive material disposed over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction;
a second electrode located between a set of spacers and in direct contact with the p-n-junction;
a phase change material located over the p-n junction and in direct contact with the second electrode; and
a third electrode disposed over a portion of the phase change material.
16. The semiconductor structure of claim 15 , wherein the first electrically conductive material is an n-type poly-silicon layer.
17. The semiconductor structure of claim 16 , wherein second electrically conductive material is a p-type poly-silicon layer.
18. The semiconductor structure of claim 15 , wherein the p-n junction and the second electrode are disposed between interlayer dielectric (ILD) regions.
19. The semiconductor structure of claim 15 , wherein the phase change material extends a length of the first electrode.
20. The semiconductor structure of claim 15 , wherein the electronic component is a poly-silicon diode.