IP Library Granted Patent US 10,374,521
Granted Patent B2
US 10,374,521 · App. 16/064,928 · Granted Aug 6, 2019

Busbar arrangement

Inventors: Jürgen Böhmer (Stein, DE); Rüdiger Kleffel (Erlangen, DE); Eberhard Ulrich Krafft (Nürnberg, DE); Andreas Nagel (Nürnberg, DE); Jan Weigel (Grossenbuch, DE)
Assignee: SIEMENS AKTIENGESELLSCHAFT
H02M7/003H01L23/5223H01L25/16H05K7/1432
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Quick Facts
Patent No.
US 10,374,521
App. No.
16/064,928
Granted
Aug 6, 2019
Kind
B2
Abstract

A busbar arrangement for making electrical contact with a semiconductor module includes at least two busbars overlapping in an overlap region and electrically insulated from one another. Each busbar includes a web having a connection element, with the webs of the busbars being arranged without an overlap. The webs are oriented such as to define a first axis which runs through the connection element of an associated one of the webs and a point of a transition of the web to the overlap region of the busbar arrangement, and which intersects a second axis which is formed by a connection between two connection elements of the webs at an angle between 0° and 45°. The busbar arrangement includes an insulating region to reduce or prevent a current in the web in a direction perpendicular to the second axis. The overlap region and the webs are each located in one plane.

Claims (24)

1. A busbar arrangement for making electrical contact with a semiconductor module, said busbar arrangement comprising:

at least two busbars overlapping one another in an overlap region and electrically insulated from one another, each of the busbars including a web having a connection element, with a web of one of the busbars and a web of another one of the busbars arranged in an absence of an overlap, said webs oriented such as to define a first axis which runs through the connection element of an associated one of the webs and a point of a transition of the associated one of the webs to the overlap region of the busbar arrangement, and which intersects a second axis which is formed by a connection between two connection elements of the webs at an angle between 0° and 45°; and

an insulating region configured to reduce or prevent a current in the web in a direction perpendicular to the second axis,

wherein the overlap region and the webs are each located in one plane.

2. A converter module, comprising:

a busbar arrangement for making electrical contact with a semiconductor module, said busbar arrangement comprising at least two busbars overlapping one another in an overlap region and electrically insulated from one another, each of the busbars including a web having a connection element, with a web of one of the busbars and a web of another one of the busbars arranged in an absence of an overlap, said webs oriented such as to define a first axis which runs through the connection element of an associated one of the webs and a point of a transition of the associated one of the webs to the overlap region of the busbar arrangement, and which intersects a second axis which is formed by a connection between two connection elements of the webs at an angle between 00 and 45°, and an insulating region configured to reduce or prevent a current in the web in a direction perpendicular to the second axis, wherein the overlap region and the webs are each located in one plane;

the semiconductor module having two direct current connections connected electrically to the connection elements of the busbar arrangement, respectively; and

a capacitor having two electrodes,

wherein the busbars of the busbar arrangement are connected electrically to the electrodes of the capacitor.

3. The busbar arrangement of claim 1 , wherein the busbars have each at least two webs, each of the webs having at least one connection element.

4. The busbar arrangement of claim 1 for connection of the semiconductor module to a capacitor, in particular in a converter.

5. The converter module of claim 2 , further comprising a further semiconductor module, wherein the direct current connections of the semiconductor modules are arranged in a parallel circuit.

6. The converter module of claim 2 , wherein the semiconductor module includes at least two series circuits of semiconductor switches and at least four direct current connections.

7. The converter module of claim 2 , wherein the insulating region is configured to reduce or prevent formation of the current in the direction perpendicular to the second axis in the transition between the web and the overlap region.

8. The converter module of claim 2 , wherein the insulating region is configured to adjoin the overlap region.

9. The converter module of claim 2 , wherein the insulating region is arranged in at least one section at a boundary between the web and the overlap region.

10. The converter module of claim 2 , wherein at least two of the webs are embodied symmetrically to one another.

11. The converter module of claim 2 , further comprising an insulating layer arranged in the overlap region between the busbars, said busbars each having at least one section in adjoining relationship to the insulating layer.

12. The converter module of claim 2 , wherein the busbars have each at least two webs, each of the webs having at least one connection element.

13. The busbar arrangement of claim 1 , wherein the insulating region is configured to reduce or prevent formation of the current in the direction perpendicular to the second axis in the transition between the web and the overlap region.

14. The busbar arrangement of claim 1 , wherein the insulating region is configured to adjoin the overlap region.

15. The busbar arrangement of claim 1 , wherein the insulating region is arranged in at least one section at a boundary between the web and the overlap region.

16. The busbar arrangement of claim 1 , wherein at least two of the webs are embodied symmetrically to one another.

17. The busbar arrangement of claim 1 , further comprising an insulating layer arranged in the overlap region between the busbars, said busbars having each at least one section in adjoining relationship to the insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2018
From: NAGEL, ANDREAS; BÖHMER, JÜRGEN; KLEFFEL, RÜDIGER; WEIGEL, JAN; KRAFFT, EBERHARD ULRICH
To: SIEMENS AKTIENGESELLSCHAFT
Reel/Frame 046168/0692 →
Priority Claims (1)
EP 15201849 · Dec 22, 2015 · regional
Continuity (1)
Related Publication 20190036461A1 · Jan 31, 2019
Cited By (2)
US 12,191,054 US 12,489,041