Adaptive multiband power amplifier apparatus
A power amplifier apparatus, includes an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current DC, based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and a power amplifier circuit having a bipolar junction transistor supplied with the first ET bias current and a power voltage to amplify the input signal, wherein an average current of the first ET bias current is controlled to be substantially constant.
1. A power amplifier apparatus, comprising:
an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current (DC), based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and
a power amplifier circuit comprising a bipolar junction transistor that is configured to receive the first ET bias current and a power voltage to amplify the input signal,
wherein an average current of the first ET bias current is controlled to be substantially constant,
wherein a ratio of an average current of the ET current and the direct current is adjusted according to a ratio parameter that is determined in advance; and
wherein the power amplifier further comprises a control circuit configured to generate a first control signal and a second control signal based on the ratio parameter, and provide the generated first and second control signals to the ET current bias circuit.
2. The power amplifier apparatus of claim 1 , wherein the control circuit comprises the ratio parameter, determined according to operating characteristics of the corresponding power amplifier circuit.
3. The power amplifier apparatus of claim 1 , wherein the ET current bias circuit comprises:
a first current source circuit configured to adjust a value of the direct current in response to the first control signal;
a second current source circuit configured to adjust a value of the ET current in response to the second control signal; and
a bias current generator configured to generate the first ET bias current by calculating the direct current and the ET current and supply the generated first ET bias current to a base of the bipolar junction transistor.
4. The power amplifier apparatus of claim 3 , wherein the bias current generator is configured to generate the first ET bias current by connecting an output node of the first current source circuit to an output node of the second current source circuit and summing the direct current and the ET current.
5. The power amplifier apparatus of claim 1 , wherein the power amplifier circuit comprises:
a power amplifier comprising the bipolar junction transistor, and the power amplifier is configured to amplify the input signal through an input terminal; and
a buffered bias circuit configured to generate a second ET bias current based on the first ET bias current, and supply the second ET bias current to a base of the bipolar junction transistor.
6. The power amplifier apparatus of claim 1 , further comprising an ET circuit configured to generate the power voltage tracking the ET voltage and supply the generated power voltage to the power amplifier circuit,
wherein the ET current bias circuit is configured to receive the power voltage from the ET circuit and generate the ET current.
7. The power amplifier apparatus of claim 1 , further comprising an envelope detection circuit configured to detect the ET voltage,
wherein the ET current bias circuit is configured to receive the ET voltage from the envelope detection circuit and generate the ET current.
8. The power amplifier apparatus of claim 1 , further comprising:
an envelope detection circuit configured to detect the ET voltage; and
an average power tracking (APT) circuit configured to generate the power voltage tracking an average voltage of the ET voltage and supply the generated power voltage to the power amplifier circuit,
wherein the ET current bias circuit is configured to receive the ET voltage from the envelope detection circuit and generate the ET current.
9. The power amplifier apparatus of claim 5 , wherein the buffered bias circuit comprises:
a current bias circuit connected between an output terminal of the ET current bias circuit and a ground;
a current amplifier current-biased by the current bias circuit and configured to amplify the first ET bias current and generate the second ET bias current; and
a ballast resistor connected to an output terminal that is configured to output the second ET bias current.
10. The power amplifier apparatus of claim 9 , wherein the ballast resistor has a resistance value that is set according to the ratio parameter.
11. The power amplifier apparatus of claim 9 , wherein the current bias circuit comprises:
a first bias resistor connected between the output terminal of the ET current bias circuit and a base of the current amplifier; and
a temperature compensation circuit connected between the base of the current amplifier and the ground and having a resistance value that is varied according to a temperature.
12. The power amplifier apparatus of claim 11 , wherein the temperature compensation circuit comprises at least two diode-connected transistors connected in series between the base of the current amplifier and the ground.
13. The power amplifier apparatus of claim 11 , wherein the temperature compensation circuit comprises at least two diodes connected in series between the base of the current amplifier and the ground.
14. A power amplifier apparatus comprising:
an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current (DC), based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and
a power amplifier circuit comprising first to n-th power amplifier circuits, wherein each of the first to n-th power amplifier circuits has a bipolar junction transistor that is configured to receive the first ET bias current and a power voltage to amplify the input signal,
wherein an average current of the first ET bias current is controlled to be substantially constant,
wherein a ratio of an average current of the ET current and the direct current is adjusted according to a ratio parameter that is determined in advance, and
wherein the power amplifier apparatus further comprises a control circuit configured to generate a first control signal and a second control signal based on the ratio parameter, and provide the generated first and second control signals to the ET current bias circuit.
15. The power amplifier apparatus of claim 14 , wherein the control circuit comprises the ratio parameter, determined according to operating characteristics of each of the first to n-th power amplifier circuits.
16. The power amplifier apparatus of claim 14 , wherein the ET current bias circuit comprises:
a first current source circuit configured to adjust a value of the direct current in response to the first control signal;
a second current source circuit configured to adjust a value of the ET current in response to the second control signal; and
a bias current generator configured to generate the first ET bias current by calculating the direct current and the ET current and supply the generated first ET bias current to a base of the bipolar junction transistor.
17. The power amplifier apparatus of claim 16 , wherein the bias current generator is configured to generate the first ET bias current by connecting an output node of the first current source circuit to an output node of the second current source circuit and summing the direct current and the ET current.
18. The power amplifier apparatus of claim 14 , wherein each of the first to n-th power amplifier circuits comprise:
a power amplifier comprising the bipolar junction transistor, and the power amplifier is configured to amplify the input signal through an input terminal; and
a buffered bias circuit configured to generate a second ET bias current based on the first ET bias current and supply the second ET bias current to a base of the bipolar junction transistor.
19. The power amplifier apparatus of claim 14 , further comprising an ET circuit configured to generate the power voltage tracking the ET voltage and supply the generated power voltage to the power amplifier circuit, wherein the ET current bias circuit is configured to receive the power voltage from the ET circuit and generate the ET current.
20. The power amplifier apparatus of claim 14 , further comprising an envelope detection circuit configured to detect the ET voltage,
wherein the ET current bias circuit is configured to receive the ET voltage from the envelope detection circuit and generate the ET current.
21. The power amplifier apparatus of claim 14 , further comprising:
an envelope detection circuit configured to detect the ET voltage; and
an average power tracking (APT) circuit configured to generate the power voltage tracking an average voltage of the ET voltage and supply the generated power voltage to the power amplifier circuit,
the ET current bias circuit is configured to receive the ET voltage from the envelope detection circuit and generate the ET current.
22. The power amplifier apparatus of claim 18 , wherein the buffered bias circuit comprises:
a current bias circuit connected between an output terminal of the ET current bias circuit and a ground;
a current amplifier current-biased by the current bias circuit and configured to amplify the first ET bias current and generate the second ET bias current; and
a ballast resistor connected to an output terminal that is configured to output the second ET bias current.
23. The power amplifier apparatus of claim 22 , wherein the ballast resistor has a resistance value that is set according to the ratio parameter.
24. The power amplifier apparatus of claim 22 , wherein the current bias circuit comprises:
a first bias resistor connected between the output terminal of the ET current bias circuit and a base of the current amplifier; and
a temperature compensation circuit connected between the base of the current amplifier and the ground and having a resistance value that is varied according to a temperature.
25. The power amplifier apparatus of claim 24 , wherein the temperature compensation circuit comprises at least two diode-connected transistors connected in series between the base of the current amplifier and the ground.
26. The power amplifier apparatus of claim 24 , wherein the temperature compensation circuit comprises at least two diodes connected in series between the base of the current amplifier and the ground.