High voltage level shifter with short propagation delay
A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.
1. A device comprising:
a blocking circuit having:
a first comparator including a first non-inverting input coupled to a first reference voltage source, a first inverting input coupled to an first signal node, and a first comparator output;
a second comparator including a second non-inverting input coupled to a second signal node, a second inverting input coupled to a second reference voltage source, and a second comparator output; and
an AND gate having a first input coupled to the first comparator output, a second input coupled to the second comparator output, and a reset output; and
a set-reset (SR) latch having a reset input coupled to the reset output of the AND gate, and a latch output associated with a high side output terminal.
2. The device of claim 1 , wherein:
the blocking circuit includes:
a third comparator including a third non-inverting input coupled to the first signal node, a third inverting input coupled to the second reference voltage source, and a third comparator output;
a fourth comparator including a fourth non-inverting input coupled to the first reference voltage source, a fourth inverting input coupled to the second signal node, and a fourth comparator output; and
a second AND gate having a third input coupled to the third comparator output, a fourth input coupled to the fourth comparator output, and a set output; and
the SR latch having a set input coupled to the set output of the second AND gate.
3. The device of claim 1 , wherein the first signal node is configured to conduct an OFF signal for turning off a high side transistor, and the second signal node is configured to conduct an ON signal for turning on the high side transistor.
4. The device of claim 1 , further comprising:
a voltage supply rail coupled to the first comparator, the second comparator, the AND gate, and the SR latch;
a first resistor coupled between the first signal node and the voltage supply rail; and
a second resistor coupled between the second signal node and the voltage supply rail.
5. The device of claim 1 , further comprising:
a voltage supply rail configured to supply a high-side floating supply (HB) voltage to the first comparator, the second comparator, the AND gate, and the SR latch,
wherein:
the second reference voltage source is configured to generate a second reference voltage lower than the HB voltage; and
the first reference voltage source is configured to generate a first reference voltage lower than the second reference voltage.
6. The device of claim 1 , further comprising:
a gate driver circuit having a gate driver input coupled to the latch output, and a gate driver output coupled to the high side output terminal.
7. A device comprising:
a blocking circuit having:
a first comparator configured to generate a first comparator output signal when a first reference voltage is less than an OFF signal; and
a second comparator configured to generate a second comparator output signal when an ON signal is less than a second reference voltage; and
a logic circuit configured to reset a gate driver signal upon detecting the first comparator output signal and the second comparator output signal.
8. The device of claim 7 , wherein:
the blocking circuit includes:
a third comparator configured to generate a third comparator output signal when the OFF signal is less than the second reference voltage; and
a fourth comparator configured to generate a fourth comparator output signal when the first reference voltage is less than the ON signal; and
the logic circuit configured to set the gate driver signal upon detecting the third comparator output signal and the fourth comparator output signal.
9. The device of claim 8 , wherein the logic circuit includes:
a first AND gate having a first input coupled to receive the first comparator output signal, a second input coupled to receive the second comparator output signal, and a reset output;
a second AND gate having a third input coupled to receive the third comparator output signal, a fourth input coupled to receive the fourth comparator output signal, and a set output; and
a set-reset (SR) latch having a reset input coupled to the reset output of the first AND gate, a set input coupled to the set output of the second AND gate, and a latch output.
10. The device of claim 7 , further comprising:
a voltage supply rail configured to supply a high-side floating supply (HB) voltage to the first comparator, the second comparator, the logic circuit,
wherein:
the second reference voltage is lower than the HB voltage; and
the first reference voltage is lower than the second reference voltage.