Packages with Si-substrate-free interposer and method forming same

1. A package of integrated circuits, the package comprising:

a plurality of dielectric layers;

a plurality of redistribution lines in each of the plurality of dielectric layers;

a through-dielectric via penetrating through the plurality of dielectric layers, wherein the through-dielectric via has a substantially straight edge penetrating through the plurality of dielectric layers;

stacked vias in the plurality of dielectric layers, wherein the stacked vias are electrically connected to each other to form a continuous electrical connection penetrating through the plurality of dielectric layers;

a plurality of bond pads over and connected to the through-dielectric via and the stacked vias;

a first dielectric layer, with the plurality of bond pads located in the first dielectric layer; and

a first device die bonded to the first dielectric layer and a first portion of the plurality of bond pads.

2. The package of claim 1 further comprising a second device die bonded to the first dielectric layer and a second portion of the plurality of bond pads through hybrid bonding, wherein the first device die and the second device die are electrically coupled to each other through the plurality of redistribution lines.

3. The package of claim 1 further comprising:

a second device die over and bonded to the first device die;

a bond pad contacting a semiconductor substrate of the second device die, wherein at least a portion of the bond pad is over the semiconductor substrate of the second device die;

a second dielectric layer, with the bond pad having at least a portion in the second dielectric layer; and

a bulk substrate over and bonded to the second dielectric layer and the bond pad.

4. The package of claim 3 , wherein the bulk substrate is formed of silicon, and no active device and passive device are formed on the bulk substrate.

5. The package of claim 3 , wherein the bond pad further extends into the semiconductor substrate of the second device die.

6. The package of claim 3 further comprising an additional plurality of bond pads comprising the bond pad, wherein the plurality of bond pads form a grid.

7. The package of claim 1 , wherein the through-dielectric via is free from horizontal interfaces therein to separate portions of the through-dielectric via in different ones of the plurality of dielectric layers from each other, and the stacked vias have distinguishable horizontal interfaces in between.

8. The package of claim 1 , wherein the through-dielectric via is a power connection, and the stacked vias are signal connections.

9. A package of integrated circuits, the package comprising:

a plurality of dielectric layers;

stacked vias penetrating through the plurality of dielectric layers, wherein the stacked vias have dual damascene structures, and the stacked vias are interconnected to form a continuous electrical connection structure, with edges of upper ones of the stacked vias flush with edges of respective lower ones of the stacked vias;

a first dielectric layer over and contacting the plurality of dielectric layers;

a first bond pad in the first dielectric layer, wherein the first bond pad is in physical contact with a top surface of the stacked vias;

a device die over the plurality of dielectric layers, wherein the device die is bonded to underlying structures through a bonding structure comprising:

dielectric-to-dielectric bonding, with a surface dielectric layer of the device die bonded to the first dielectric layer through Si—O—Si bonds; and

copper-to-copper bonding, with copper of the first bond pad bonded to and physically joined to copper of an additional bond pad in the device die; and

a die stack over the device die.

10. The package of claim 9 further comprising a through-dielectric via penetrating through the plurality of dielectric layers, wherein the die stack is bonded to the through-dielectric via through an additional bonding structure comprising dielectric-to-dielectric bonding and metal-to-metal bonding.

11. The package of claim 10 , wherein the through-dielectric via comprises portions extending into different ones of the plurality of dielectric layers, with no distinguishable interfaces between the portions.

12. The package of claim 9 further comprising:

a bulk substrate over and bonded to the device die.

13. The package of claim 12 further comprising:

a second bond pad contacting a semiconductor substrate of the device die, wherein at least a portion of the second bond pad is over the semiconductor substrate of the device die; and

a second dielectric layer, with the second bond pad having at least a portion in the second dielectric layer.

14. The package of claim 12 , wherein the bulk substrate is formed of silicon, and no active device and passive device are formed on the bulk substrate.

15. A package of integrated circuits, the package comprising:

a plurality of dielectric layers;

a passive device in the plurality of dielectric layers;

a through-dielectric via penetrating through the plurality of dielectric layers;

stacked vias in the plurality of dielectric layers, wherein the stacked vias are electrically connected to each other to form a continuous electrical connection penetrating through the plurality of dielectric layers;

a first bond pad over and contacting a top via in the stacked vias;

a second bond pad over and contacting the through-dielectric via; and

a device die over and bonded to both the first bond pad and the second bond pad.

16. The package of claim 15 , wherein the device die comprises a semiconductor substrate, and the package further comprises a third bond pad extending to an intermediate level of the semiconductor substrate, and wherein the intermediate level is between a top surface and a bottom surface of the semiconductor substrate.

17. The package of claim 16 , wherein the bottom surface of the third bond pad contacts a surface of the semiconductor substrate to form an interface.

18. The package of claim 16 further comprising:

an encapsulant encapsulating the device die therein; and

a dielectric layer over and contacting the top surface of the semiconductor substrate and a top surface of the encapsulant, wherein the third bond pad further extends into the dielectric layer.

19. The package of claim 16 further comprising a bulk substrate bonded to the third bond pad.

20. The package of claim 19 , wherein the bulk substrate further comprises:

an additional dielectric layer at a bottom surface of the semiconductor substrate; and

an additional bond pad in the additional dielectric layer, wherein the additional bond pad is physically bonded to the third bond pad.