Semiconductor memory device and a manufacturing method thereof
A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
1. A manufacturing method of a semiconductor memory device, comprising:
providing a semiconductor substrate, wherein a shallow trench isolation is formed in the semiconductor substrate and defines a plurality of active regions;
performing a first etching process for forming a bit line contact opening in the semiconductor substrate, wherein the bit line contact opening is formed corresponding and exposes one of the active regions, and an edge of the bit line contact opening has an under-cut structure;
forming a bit line structure on the semiconductor substrate, wherein the bit line structure is partially disposed in the bit line contact opening and in contact with one of the active regions corresponding to the bit line contact opening, and a bottom width of the bit line contact opening is greater than a top width of the bit line contact opening; and
forming an isolation structure in the under-cut structure of the bit line contact opening,
wherein a bottom of the isolation structure is wider than a top of the isolation structure,
wherein a manufacturing method of the isolation structure comprises:
forming an insulating layer on the semiconductor substrate and in the bit line contact opening, wherein the under-cut structure of the bit line contact opening is filled with the insulating layer; and
performing a second etching process to the insulating layer for removing the insulating layer outside the bit line contact opening and a portion of the insulating layer in the bit line contact opening, so as to form the isolation structure in the under-cut structure.
2. The manufacturing method of the semiconductor memory device according to claim 1 , wherein the second etching process is performed before the bit line structure is formed.
3. The manufacturing method of the semiconductor memory device according to claim 1 , further comprising:
forming a spacer layer on the semiconductor substrate and the bit line structure, wherein the spacer layer is partially formed in the bit line contact opening, and a portion of the spacer layer is formed between the isolation structure and the bit line structure.
4. The manufacturing method of the semiconductor memory device according to claim 1 , wherein the under-cut structure of the bit line contact opening is formed in the shallow trench isolation.