Group IIIA-N HEMT with a tunnel diode in the gate stack
An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.
1. A method of forming a transistor, comprising:
providing n-GaN layer on an InGaN layer on a p-GaN layer on a Group IIIA-N barrier layer on an active layer on a substrate;
forming at least one isolation region through said barrier layer to provide at least one isolated active area comprising said barrier layer on said active layer;
defining a tunnel diode by patterning said n-GaN layer;
forming a gate electrode over said n-GaN layer;
forming a drain having a drain contact on said barrier layer, and
forming a source having a source contact on said barrier layer.
2. The method of claim 1 , wherein said InGaN layer is doped n-type.
3. The method of claim 1 , wherein said InGaN layer is doped p-type.
4. The method of claim 1 , wherein said InGaN layer includes a linearly graded In concentration in a thickness direction for reducing a barrier voltage of said tunnel diode.
5. The method of claim 1 , wherein said InGaN layer has a thickness in a range between about 3.5 nm and about 10 nm.
6. The method of claim 1 , wherein said gate electrode comprises titanium or aluminum.
7. The method of claim 1 , wherein said transistor is part of an integrated circuit (IC) formed in and on said substrate.
8. The method of claim 1 , wherein said transistor is a first transistor and further comprising at least a second transistor, further comprising providing a different thickness of said InGaN layer for said first transistor and said second transistor.
9. The method of claim 8 , wherein said step of providing said different thickness comprises selectively etching said n-GaN layer and said InGaN layer so that said second transistor lacks said tunnel diode while said first transistor includes said n-GaN layer and said InGaN layer so that it includes said tunnel diode.
10. A method of forming an electronic device, comprising:
forming a gate stack over a first group IIIA-N layer, the first group IIIA-N layer being located on a second group IIIA-N layer, and the gate stack having a topmost n-type group IIIA-N layer;
forming a gate electrode directly on the topmost n-type group IIIA-N layer.
11. The method of claim 10 , wherein said n-type layer comprises silicon.
12. The method of claim 10 , wherein said gate stack comprises an InGaN layer between two GaN layers.
13. The method of claim 10 , wherein said gate electrode comprises Ti or Al.
14. The method of claim 10 , further comprising forming source and drain electrodes over said first group IIIA-N layer simultaneously with said gate electrode.
15. The method of claim 10 , wherein said gate stack is a first gate stack of a first transistor, and further comprising forming a second gate stack of a second transistor on the first group IIIA-N layer, the first gate stack including a first ternary semiconductor layer between two binary semiconductor layers, and the first gate stack including a second ternary semiconductor layer between two binary semiconductor layers, wherein the first and second ternary semiconductor layers have different thicknesses.
16. A method of forming an electronic device, comprising:
forming a gate stack comprising a tunnel diode on a group IIIA-N barrier layer;
forming a gate electrode over the gate stack; and
forming source and drain electrodes on the barrier layer from a same metal layer as the gate electrode.
17. The method of claim 16 , wherein said gate stack includes a topmost group IIIA-N layer doped with silicon.
18. The method of claim 16 , wherein said gate stack comprises an InGaN layer between an n-type GaN layer and a p-type GaN layer, said gate electrode being formed directly on said n-type GaN layer.
19. The method of claim 16 , wherein said gate electrode comprises Ti or Al.
20. The method of claim 10 , further comprising forming source and drain electrodes on the first group IIIA-N layer from a same metal layer as the gate electrode.