Spin transfer torque memory (STTM), methods of forming the same using a non-conformal insulator, and devices including the same
Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.
1. An integrated circuit device comprising at least one spin transfer torque memory (STTM) element, wherein:
the STTM element comprises a substrate, a conductive layer on the substrate, and a material stack on the conductive layer, at least a portion of the material stack defining a magnetic tunnel junction (MTJ) including a fixed magnetic layer, a first dielectric layer comprising a first dielectric material, and a free magnetic layer, the magnetic tunnel junction comprising at least one sidewall, wherein a re-deposited layer is present on at least one of said sidewalls, the re-deposited layer comprising components of at least one of said fixed magnetic layer, dielectric layer, and free magnetic layer; and
a gap is present in the re-deposited layer, the gap interrupting the electrical continuity of the re-deposited layer and comprising a second dielectric material.
2. The integrated circuit of claim 1 , wherein said first dielectric material comprises a dielectric oxide.
3. The integrated circuit of claim 2 , wherein said first dielectric material comprises magnesium oxide or aluminum oxide.
4. The integrated circuit of claim 1 , wherein said STTM element is a planar STTM element or a perpendicular STTM element.
5. The integrated circuit of claim 1 , wherein:
a lower surface of said first dielectric layer of said MTJ is spaced from an upper surface of said conductive layer by a distance, d;
said non-conformal second dielectric layer has a thickness tin a region above said conductive layer; and
t is less than d.
6. The integrated circuit of claim 1 , further comprising a crown of said second dielectric material on said magnetic tunnel junction.
7. The integrated circuit of claim 1 , further comprising a shim layer between said conductive layer and said fixed magnetic layer.
8. An integrated circuit device comprising at least one spin transfer torque memory (STTM) element, wherein:
the STTM element comprises a substrate that includes at least one groove, a conductive layer that is disposed on the substrate and present within said at least one groove, and a material stack on the conductive layer, at least a portion of the material stack defining a magnetic tunnel junction (MTJ) that includes a fixed magnetic layer, a first dielectric layer comprising a first dielectric material, and a free magnetic layer, the magnetic tunnel junction comprising at least one sidewall, wherein a re-deposited layer is present on at least one of said sidewalls, the re-deposited layer comprising components of at least one of said fixed magnetic layer, dielectric layer, and free magnetic layer;
a gap is present in the re-deposited layer, the gap interrupting the electrical continuity of the re-deposited layer; and
the width of the conductive layer is greater than the width of said MTJ in at least one dimension.
9. An integrated circuit device comprising at least one spin transfer torque memory (STTM) element, wherein:
the STTM element comprises a substrate, a conductive layer on the substrate, and a material stack on the conductive layer, at least a portion of the material stack defining a magnetic tunnel junction (MTJ) including a fixed magnetic layer, a first dielectric layer having a thickness and comprising a first dielectric material, and a free magnetic layer, the magnetic tunnel junction comprising at least one sidewall, wherein a re-deposited layer is present on at least one of said sidewalls, the re-deposited layer comprising components of at least one of said fixed magnetic layer, dielectric layer, and free magnetic layer; and
a gap is present in the re-deposited layer, wherein said gap is formed in a region of the re-deposited layer proximate said first dielectric layer, interrupts the electrical continuity of the re-deposited layer, and spans an entirety of the thickness of the first dielectric layer.