Systolic random number generator
Systems and methods for a random number generator including a systolic array to receive a plurality of first inputs, and to provide a random number output. In one embodiment, the systolic array can be arranged in two or greater dimensions, and each cell of the array comprises a ring oscillator. Data is read from a random access memory to provide the inputs to the systolic array. A linear feedback shift register receives the random number output as a feedback signal used to address the memory to read data to provide as the inputs to the systolic array.
1. A random number generator comprising:
a systolic array comprising a plurality of cells, wherein each cell comprises an oscillator, and the systolic array is configured to provide a random number output; and
memory configured to provide inputs to the systolic array, wherein a feedback signal based on the random number output is used to address the memory to select the inputs.
2. The random number generator of claim 1 , wherein each cell further comprises a flip-flop coupled to receive an input signal from the oscillator, and each cell further comprises an exclusive OR gate coupled to receive an output from the flip-flop.
3. The random number generator of claim 2 , wherein the exclusive OR gate is further coupled to receive inputs from two adjacent cells in the systolic array.
4. The random number generator of claim 2 , wherein the flip-flop is a first flip-flop, and wherein each cell further comprises a second flip-flop coupled to receive an input from the exclusive OR gate and to provide an output to an adjacent cell in the systolic array.
5. The random number generator of claim 1 , wherein the memory is configured for use as a physical unclonable function.
6. The random number generator of claim 1 , further comprising a clock configured to provide a signal to control providing of the feedback signal to the memory.
7. The random number generator of claim 1 , further comprising a register configured to receive the inputs from the memory, wherein the register receives a clock signal to control providing the inputs to the systolic array.
8. The random number generator of claim 1 , wherein a clock signal is coupled to a shift register to control providing the address to the memory.
9. The random number generator of claim 1 , further comprising at least one exclusive OR gate configured to receive outputs from at least two cells in the systolic array, wherein an output of the at least one exclusive OR gate provides the random number output.
10. The random number generator of claim 9 , further comprising at least one output register coupled to receive and store the random number output from the at least one exclusive OR gate, wherein the at least one output register provides the random number output to a shift register as the feedback signal.
11. A system comprising:
a systolic array configured to receive a plurality of inputs, and to provide a random number output; and
memory configured to provide the inputs to the systolic array, and further coupled to receive a signal based on the random number output, wherein the signal is used for selecting the inputs provided to the systolic array.
12. The system of claim 11 , wherein the systolic array comprises a plurality of cells, each cell including an oscillator.
13. The system of claim 11 , further comprising a shift register configured to:
receive the random number output; and
provide an output used for addressing the memory to select the inputs provided to the systolic array.
14. A random number generator comprising:
an output register; and
a systolic array configured to provide a random number value to the output register, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator.
15. The random number generator of claim 14 , wherein each cell further comprises a flip-flop coupled to receive a signal from the oscillator.
16. The random number generator of claim 14 , wherein each cell further comprises a flip-flop, and an exclusive OR gate coupled to receive an output from the flip-flop.
17. The random number generator of claim 14 , wherein each cell further comprises a flip-flop coupled to receive a signal from an exclusive OR gate.
18. A random number generator comprising:
a physical unclonable function; and
a systolic array configured to receive at least one input from the physical unclonable function, and to provide a random number as an output.
19. The random number generator of claim 18 , wherein at power-up of the random number generator, data from the physical unclonable function is read as initial seed values for the systolic array.
20. The random number generator of claim 18 , wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator.
21. The random number generator of claim 20 , wherein the oscillator is a free-running asynchronous oscillator.
22. The random number generator of claim 21 , wherein each cell further comprises a flip-flop that receives an input signal from the oscillator.
23. The random number generator of claim 20 , wherein the physical unclonable function is a memory, the memory provides the at least one input to the systolic array, and the at least one input is selected by addressing the memory based on the random number output by the systolic array.
24. The random number generator of claim 20 , wherein the oscillator is a ring oscillator.
25. The random number generator of claim 21 , wherein the free-running asynchronous oscillator is a ring oscillator.