GOA drive unit and drive circuit

1. A GOA drive unit, comprising a pull-up part, a pull-up control part, a key pull-down part, a pull-down holding part, and a boost capacitor, wherein:

the pull-down holding part comprises a mirrored circuit structure connected through a source and a drain that are of a bridge transistor,

wherein the mirrored circuit structure comprises: a first pull-down transistor and a second pull-down transistor that are configured to maintain a low voltage at a control signal input end of the pull-up part, a third pull-down transistor and a fourth pull-down transistor that are configured to maintain a low voltage at a gate scanning signal output end of the pull-up part, a fifth pull-down transistor that is configured to maintain a low voltage at gate electrodes of the first pull-down transistor and the third pull-down transistor, and a sixth pull-down transistor that is configured to maintain a low voltage at gate electrodes of the second pull-down transistor and the fourth pull-down transistor,

wherein a drain of the fifth pull-down transistor is coupled with the gate electrodes of the first pull-down transistor and the third pull-down transistor, a drain of the sixth pull-down transistor is coupled with the gate electrodes of the second pulldown transistor and the fourth pull-down transistor, gate electrodes of the fifth pulldown transistor and the sixth pull-down transistor are coupled together at the control signal input end of the pull-up part, and

sources of all the pull-down transistors are coupled at a first pull-down voltage;

wherein the mirrored circuit structure further comprises a first alternate control circuit and a second alternate control circuit that are mirrored,

wherein the first alternate control circuit comprises:

a seventh transistor, wherein a gate electrode and a drain of the seventh transistor are coupled together and are configured to receive a first alternate control signal;

an eighth transistor, wherein a gate electrode and a drain of the eighth transistor are coupled with a source and the drain of the seventh transistor respectively;

a ninth transistor, wherein a drain and a source of the ninth transistor are coupled with the drain and a source of the eighth transistor respectively, and the gate electrode of the ninth transistor is configured to receive a second alternate control signal; and

a tenth transistor, wherein a drain of the tenth transistor is coupled with the gate of the eighth transistor, and a gate electrode and a source of the tenth transistor are coupled with a gate electrode and a source of the fifth pull-down transistor respectively; and

wherein the second alternate control circuit has a mirrored structure of the first alternate control circuit, and input ends of a first alternate control signal and a second alternate control signal of the second alternate control circuit are interchanged; and

the first alternate control signal and the second alternate control signal are high and low alternately.

2. The GOA drive unit according to claim 1 wherein the sources of the fifth pull-down transistor and the sixth pull-down transistor are coupled at a second pull-down voltage, wherein the second pull-down voltage is less than the first pull-down voltage.

3. The GOA drive unit according to claim 1 wherein drains of the first pull-down transistor and the second pull-down transistor are coupled together at the control signal input end of the pull-up part, and drains of the third pull-down transistor and the fourth pull-down transistor are coupled together at the gate scanning signal output end of the pull-up part.

4. The GOA drive unit according to claim 1 , wherein a frequency of the alternate control signal is less than a frequency of a scanning clock signal of the GOA drive unit.

5. The GOA drive unit according to claim 1 , further comprising a download element, wherein the download element comprises a download transistor, wherein a gate electrode of the download transistor is coupled with the control signal input end of the pull-up part, a drain of the download transistor is coupled with a clock signal input end of the pull-up part, and a source of the download transistor is configured to generate a download signal that acts on a next-level GOA drive unit.

6. A GOA drive circuit formed by a GOA drive unit by cascading, wherein:

the GOA drive unit comprises a pull-up part, a pull-up control part, a key pull-down part, a pull-down holding part, and a boost capacitor, wherein the pull-down holding part comprises a mirrored circuit structure connected through a source and a drain that are of a bridge transistor,

wherein the mirrored circuit structure comprises: a first pull-down transistor and a second pull-down transistor that are configured to maintain a low voltage at a control signal input end of the pull-up part, a third pull-down transistor and a fourth pull-down transistor that are configured to maintain a low voltage at a gate scanning signal output end of the pull-up part, a fifth pull-down transistor that is configured to maintain a low voltage at gate electrodes of the first pull-down transistor and the third pull-down transistor, and a sixth pull-down transistor that is configured to maintain a low voltage at gate electrodes of the second pull-down transistor and the fourth pull-down transistor,

wherein a drain of the fifth pull-down transistor is coupled with the gate electrodes of the first pull-down transistor and the third pull-down transistor, a drain of the sixth pull-down transistor is coupled with the gate electrodes of the second pulldown transistor and the fourth pull-down transistor, gate electrodes of the fifth pulldown transistor and the sixth pull-down transistor are coupled together at the control signal input end of the pull-up part, and

sources of all the pull-down transistors are coupled at a first pull-down voltage;

wherein the mirrored circuit structure further comprises a first alternate control circuit and a second alternate control circuit that are mirrored,

wherein the first alternate control circuit comprises:

a seventh transistor, wherein a gate electrode and a drain of the seventh transistor are coupled together and are configured to receive a first alternate control signal;

an eighth transistor, wherein a gate electrode and a drain of the eighth transistor are coupled with a source and the drain of the seventh transistor respectively;

a ninth transistor, wherein a drain and a source of the ninth transistor are coupled with the drain and a source of the eighth transistor respectively, and the gate electrode of the ninth transistor is configured to receive a second alternate control signal; and

a tenth transistor, wherein a drain of the tenth transistor is coupled with the gate of the eighth transistor, and a gate electrode and a source of the tenth transistor are coupled with a gate electrode and a source of the fifth pull-down transistor respectively; and

wherein the second alternate control circuit has a mirrored structure of the first alternate control circuit, and input ends of a first alternate control signal and a second alternate control signal of the second alternate control circuit are interchanged; and

the first alternate control signal and the second alternate control signal are high and low alternately,

the GOA drive unit further comprises a download element, wherein the download element comprises a download transistor, wherein a gate electrode of the download transistor is coupled with the control signal input end of the pull-up part, a drain of the download transistor is coupled with a clock signal input end of the pull-up part, and a source of the download transistor is configured to generate a download signal that acts on a next-level GOA drive unit; and

the GOA drive circuit inputs, into each GOA drive unit by means of interlacing, two scanning clock signals that have an equal frequency and reverse phases.

7. A GOA drive unit, comprising a pull-up part, a pull-up control part, a key pull-down part, a pull-down holding part, and a boost capacitor, wherein the pull-down holding part comprises a mirrored circuit structure,

wherein the mirrored circuit structure comprises: a first pull-down transistor and a second pull-down transistor that are configured to maintain a low voltage at a control signal input end of the pull-up part, a third pull-down transistor and a fourth pull-down transistor that are configured to maintain a low voltage at a gate scanning signal output end of the pull-up part, a fifth pull-down transistor that is configured to maintain a low voltage at gate electrodes of the first pull-down transistor and the third pull-down transistor, and a sixth pull-down transistor that is configured to maintain a low voltage at gate electrodes of the second pull-down transistor and the fourth pull-down transistor,

wherein a drain of the fifth pull-down transistor is coupled with the gate electrodes of the first pull-down transistor and the third pull-down transistor, a drain of the sixth pull-down transistor is coupled with the gate electrodes of the second pulldown transistor and the fourth pull-down transistor, and gate electrodes of the fifth pull-down transistor and the sixth pull-down transistor are coupled together at the control signal input end of the pull-up part;

sources of all the pull-down transistors are coupled at a first pull-down voltage; and

drains of the first pull-down transistor and the second pull-down transistor are coupled together at the control signal input end of the pull-up part, and drains of the third pull-down transistor and the fourth pull-down transistor are coupled together at the gate scanning signal output end of the pull-up part; and

the mirrored circuit structure further comprises a first alternate control circuit and a second alternate control circuit that are mirrored,

wherein the first alternate control circuit comprises:

a seventh transistor, wherein a gate electrode and a drain of the seventh transistor are coupled together and are configured to receive a first alternate control signal;

an eighth transistor, wherein a gate electrode and a drain of the eighth transistor are coupled with a source and the drain of the seventh transistor respectively;

a ninth transistor, wherein a drain and a source of the ninth transistor are coupled with the drain and a source of the eighth transistor respectively, and a gate electrode of the ninth transistor is configured to receive a second alternate control signal; and

a tenth transistor, wherein a drain of the tenth transistor is coupled with the gate electrode of the eighth transistor, and a gate electrode and a source of the tenth transistor are coupled with a gate electrode and a source of the fifth pull-down transistor respectively; and

the second alternate control circuit has a mirrored structure of the first alternate control circuit, and input ends of a first alternate control signal and a second alternate control signal of the second alternate control circuit are interchanged; and

the first alternate control signal and the second alternate control signal are high and low alternately.

8. The GOA drive unit according to claim 7 , further comprising a download element, wherein the download element comprises a download transistor, wherein a gate electrode of the download transistor is coupled with the control signal input end of the pull-up part, a drain of the download transistor is coupled with a clock signal input end of the pull-up part, and a source of the download transistor is configured to generate a download signal that acts on a next-level GOA drive unit.