Binary metallization structure for nanoscale dual damascene interconnects
A structure is provided that includes a lower interconnect level that includes a first interconnect dielectric material layer having an opening that contains a first bimetallization interconnect structure. An upper interconnect level is located above the lower interconnect level. The upper interconnect level includes a second interconnect dielectric material layer having a combined via/line opening, wherein the line portion of the combined via/line opening contains a second bimetallization interconnect structure. In accordance with the present application, the first and second bimetallization interconnect structures comprises a first electrically conductive structure composed of a first electrically conductive metal or metal alloy material having a first bulk resistivity surrounding a second electrically conductive structure composed of a second electrically conductive metal or metal alloy material having a second bulk resistivity that is less than the first bulk resistivity and a grain size greater than 10 nm.
1. A method of forming a semiconductor structure, the method comprising:
forming a lower interconnect level comprising a first interconnect dielectric material layer having an opening that contains a first bimetallization interconnect structure embedded therein; and
forming an upper interconnect level above the lower interconnect level, the upper interconnect level comprises a second interconnect dielectric material layer having a combined via/line opening, wherein the line portion of the combined via/line opening contains a second bimetallization interconnect structure embedded therein, wherein the first and second bimetallization interconnect structures comprise a first electrically conductive structure composed of a first electrically conductive metal or metal alloy material having a first bulk resistivity surrounding a second electrically conductive structure composed of a second electrically conductive metal or metal alloy material having a second bulk resistivity that is less than the first bulk resistivity and a grain size greater than 10 nm.
2. The method of claim 1 , wherein the forming the lower interconnect level comprises:
forming a nucleation layer in at least the opening present in the first interconnect dielectric material layer;
forming a first electrically conductive metal or metal alloy layer having the first bulk resistivity on the nucleation layer;
forming a second electrically conductive metal or metal alloy layer having the second bulk resistivity and a first grain size that is less than the grain size of the second electrically conductive structure by utilizing a high biased physical vapor deposition process;
performing an anneal to convert the second electrically conductive metal or metal alloy layer into a modified second electrically conductive metal or metal alloy having the second bulk resistivity and the grain size of the second electrically conductive structure; and
performing a planarization process.
3. The method of claim 2 , wherein the steps of forming the second electrically conductive metal or metal alloy layer and performing the anneal are repeated at least one more time.
4. The method of claim 1 , further comprising forming a dielectric capping layer between the first and second interconnect dielectric material layers.
5. The method of claim 1 , wherein the forming the upper interconnect level comprises:
forming a nucleation layer in the combined via/line opening;
removing the nucleation layer from a bottom portion of the via portion of the combined via/line opening;
forming a recessed first electrically conductive metal or metal alloy material in the via portion of the combined via/line opening;
forming a first electrically conductive metal or metal alloy layer having the first bulk resistivity in the line portion of the combined via/line opening;
forming a second electrically conductive metal or metal alloy layer having the second bulk resistivity and a first grain size that is less than the grain size of the second electrically conductive structure by utilizing a high biased physical vapor deposition process;
performing an anneal to convert the second electrically conductive metal or metal alloy layer into a modified second electrically conductive metal or metal alloy having the second bulk resistivity and the grain size of the another second electrically conductive structure; and
performing a planarization process.
6. The method of claim 1 , further comprising forming a dielectric capping layer on the upper interconnect level.
7. The method of claim 1 , wherein the first bulk resistivity is from 3.5 μΩ·cm to 8.0 μΩ·cm, wherein μΩ equals microohms.
8. The method of claim 7 , wherein the first electrically conductive metal or metal alloy material is composed of cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), tungsten (W), nickel (Ni), osmium (Os), palladium (Pd), platinum (Pt) or alloys thereof.
9. The method of claim 1 , wherein the second bulk resistivity is from 1.5 μΩ·cm to 3.0 μΩ·cm, wherein μΩ equals microohms.
10. The method of claim 9 , wherein second electrically conductive metal or metal alloy material comprises copper (Cu), aluminum (Al), or a copper-aluminum (Cu—Al) alloy.