3D IC package with RDL interposer and related method

1. A method of forming a three dimensional (3D) integrated circuit (IC) package, the method comprising:

providing an IC bottom die wafer including a plurality of IC bottom dies therein, each IC bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of exposed bottom die interconnects surrounded by a back side dielectric layer;

coupling a first carrier to the front device side of the IC bottom die wafer;

creating an interposer including a redistribution layer (RDL) for each IC bottom die in the IC bottom die wafer, the interposer having a front side, a back side and a second carrier coupled to the back side thereof, the RDL including a plurality of wiring layers, the wiring layers extending from back side RDL interconnects on the back side of the interposer to front side RDL interconnects on the front side of interposer;

hybrid bonding the front side of the interposer to the back side of the IC bottom die wafer, wherein for each respective IC bottom die, at least a portion of the front side RDL interconnects operatively couple to the plurality of exposed bottom die interconnects of the respective IC bottom die at a first location of the respective IC bottom die;

removing the second carrier from the interposer, exposing the back side RDL interconnects at a second location;

forming an under bump metallization (UBM) on the exposed back side RDL interconnects at the second location;

removing the first carrier and dicing the IC bottom die wafer with the interposer into the plurality of IC bottom dies, each IC bottom die including a respective RDL of the interposer and a respective UBM;

providing an IC top die including a plurality of top die interconnects; and

forming the 3D IC package by coupling the plurality of top die interconnects of the IC top die to the UBM on a selected IC bottom die.

2. The method of claim 1 , further comprising, prior to the hybrid bonding:

etching to reveal an extent of the plurality of bottom die interconnects of each IC bottom die on the back interconnect side of the IC bottom die wafer;

depositing the back side dielectric layer over the extents of the plurality of bottom die interconnects; and

planarizing the back side dielectric layer and the plurality of bottom die interconnects, exposing the plurality of bottom die interconnects.

3. The method of claim 2 , further comprising adding a pad layer to the IC bottom die wafer prior to the etching to reveal, the pad layer including the plurality of bottom die interconnects.

4. The method of claim 1 , wherein the plurality of top die interconnects of the IC top die include a micropillar arrangement configured to electrically couple to the UBM of the selected IC bottom die.

5. The method of claim 1 , wherein the plurality bottom die interconnects of the IC bottom die wafer include through semiconductor vias.

6. The method of claim 1 , wherein the hybrid bonding includes:

plasma activating the back side dielectric layer about the plurality of exposed bottom die interconnects and a dielectric layer about the front side RDL interconnects of the interposer;

contacting the front side of the interposer to the back interconnect side of the IC bottom die wafer, bonding the back side dielectric layer to the dielectric layer about the front side RDL interconnects of the interposer; and

annealing to cause the front side RDL interconnects diffuse with corresponding ones of the plurality of exposed bottom die interconnects.

7. The method of claim 1 , wherein the back side RDL interconnects have a larger pitch than the front side RDL interconnects.

8. The method of claim 1 , wherein the first location does not overlap the second location.