High-electron-mobility transistors with counter-doped dopant diffusion barrier
III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.
1. A transistor, comprising:
an active region within a fin of a first III-V semiconductor material; and
a sub-fin comprising one or more second III-V semiconductor materials, having a different III-V alloy composition than the first III-V semiconductor material, the sub-fin between the fin and a substrate comprising silicon, wherein a first portion of the sub-fin between the substrate and a second portion of the sub-fin comprises a higher concentration of non-silicon impurities than the second portion.
2. The transistor of claim 1 , wherein the first portion of the sub-fin comprises a concentration of silicon impurities that is at least an order of magnitude higher than that of the second portion.
3. The transistor of claim 1 , wherein the active region comprises III-V semiconductor material that is between a pair of doped semiconductor source/drain regions; and
further comprising:
a gate electrode disposed over the active region; and
a pair of source/drain contacts coupled to the pair of source/drain regions.
4. The transistor of claim 3 , wherein:
the pair of source/drains are n-type conductivity; and
the non-silicon impurities comprise acceptor impurities.
5. The transistor of claim 4 , wherein the acceptor impurities comprise at least one of C, Zn, Be, or Mg.
6. The transistor of claim 1 , wherein
a concentration of the non-silicon impurities within the first portion of the sub-fin is over 1e18 atoms/cm 3 ; and
a concentration of the non-silicon impurities within the second portion of the sub-fin is below 1e18 atoms/cm 3 .
7. The transistor of claim 1 , wherein:
the concentration of silicon or non-silicon impurities within the fin is below 1e18 atoms/cm 3 .
8. The transistor of claim 7 , wherein:
the concentration of the non-silicon impurities within the first portion of the sub-fin is at least 5e18 atoms/cm 3 .
9. The transistor of claim 1 , wherein:
the sub-fin extends to a height from an interface with the substrate; and
the first portion of the sub-fin extends from the interface to no more than 25% of the sub-fin height.
10. The transistor of claim 9 , wherein:
the sub-fin extends to a height from the interface with the substrate of 200-250 nm; and
the first portion of the sub-fin extends from the interface a maximum of 20-50 nm.
11. The transistor of claim 1 , wherein:
the fin structure further comprises a first III-V semiconductor material; and
the base portion and second portion of the sub-fin structure further comprise a second III-V semiconductor material.
12. The transistor of claim 11 , wherein:
the first III-V semiconductor comprises a first of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP; and
at least one of the first portion and second portion of the sub-fin comprises a second of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP.
13. A device including integrated circuitry, comprising:
a plurality of n-type finFETs, each including:
an active region of a III-V semiconductor fin between a pair of doped semiconductor source/drain regions;
a sub-fin comprising one or more III-V semiconductor materials between the fin and a substrate comprising silicon, wherein a first portion of the sub-fin between the substrate and a second portion of the sub-fin comprises a higher concentration of non-silicon impurities than the second portion;
a gate electrode over the active region; and
a pair of source/drain contacts coupled to the pair of source/drain regions; and
a plurality of p-type finFETs electrically coupled to the plurality of n-type finFETs.
14. The device of claim 13 , wherein the plurality of p-type finFETs each include active regions comprising a group IV semiconductor material.
15. The device of claim 13 , wherein the plurality of p-type finFETs each include active regions comprising a third III-V semiconductor material disposed over a sub-fin of III-V semiconductor material substantially free of the non-silicon impurities.