IP Library Granted Patent US 10,389,112
Granted Patent B2
US 10,389,112 · App. 15/255,148 · Granted Aug 20, 2019

Device and method for generating duty cycle

Inventors: Ting-Hsu Chien (Yilan County, TW); Chih-Wen Cheng (New Taipei, TW); Jeng-Hung Tsai (Santa Clara, CA)
Assignees: GLOBAL UNICHIP CORPORATION; TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H02J1/00H02M3/158H03K5/1565H03L7/0812
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Quick Facts
Patent No.
US 10,389,112
App. No.
15/255,148
Granted
Aug 20, 2019
Kind
B2
Abstract

A device for generating a duty cycle includes a converter, a corrector, and a control circuit. The converter is configured to generate a first output signal having a duty cycle to an output terminal according to an input signal. The corrector is coupled to the output terminal, and is configured to adjust the duty cycle of the first output signal according to a control signal. The converter is coupled in parallel with the corrector and between a first power source and a second power source. The control circuit is coupled to the output terminal, and is configured to generate the control signal according to the first output signal and a reference signal.

Claims (36)

1. A device for generating a duty cycle ratio for a clock, comprising:

a converter configured to generate a first output signal having the duty cycle ratio to an output terminal according to an input signal;

a corrector coupled to the output terminal, and configured to adjust the duty cycle ratio of the first output signal according to a single control signal, wherein the converter is coupled in parallel with the corrector and between a first power source and a second power source, wherein the corrector comprises: a first current source circuit directly coupled between the first power source and the output terminal, and configured to generate a first current; and a second current source circuit directly coupled between the output terminal and the second power source, and configured to generate a second current; wherein only the single control signal is transferred to the corrector to control both the first current source circuit and the second current source circuit to generate and directly inject the first current and the second current with different current values to the output terminal to adjust the duty cycle ratio or the first output signal; and

a control circuit coupled to the output terminal, and configured to generate the control signal according to the first output signal and a reference signal.

2. The device of claim 1 , wherein the converter comprises:

a first transistor coupled between the first power source and the output terminal; and

a second transistor coupled between the output terminal and the second power source,

wherein the first transistor and the second transistor are configured to output the first output signal to the output terminal according to the input signal.

3. The device of claim 1 , wherein the second current flows from the output terminal to the second power source.

4. The device of claim 1 , wherein the control circuit comprises:

a comparator configured to compare the first output signal with the reference signal to generate the control signal to an output node; and

an output capacitor coupled to the output node.

5. The device of claim 4 , further comprising:

a buffer coupled to the output terminal, and configured to generate a second output signal according to the first output signal,

wherein the comparator is further configured to compare the second output signal with the reference signal to generate the control signal.

6. The device of claim 1 , wherein the corrector is configured to generate at least one signal to the output terminal to adjust the duty cycle ratio of the first output signal, and the at least one signal does not flow through the converter.

7. A device for generating a duty cycle ratio for a clock, comprising:

a first transistor;

a second transistor configured to cooperate with the first transistor to generate an output signal having the duty cycle ratio to an output terminal according to an input signal; and

a corrector configured to generate at least one current to the output terminal in response to the output signal according to a single control signal, to adjust the duty cycle ratio of the output signal, wherein the corrector comprises: a first current source circuit directly coupled between the first power source and the output terminal, and configured to generate a first current; and a second current source circuit directly coupled between the output terminal and the second power source, and configured to generate a second current; wherein only the single control signal is transferred to the corrector to control both the first current source circuit and the second current source circuit to generate and directly inject the first current and the second current with different current values to the output terminal to adjust the duty cycle ratio of the first output signal,

wherein the at least one current is configured to be not flowing through the first transistor and the second transistor.

8. The device of claim 7 , wherein the second current flows from the output terminal to the second power source.

9. The device of claim 8 , further comprising:

a control circuit coupled to the output terminal, and configured to generate the control signal according to the output signal and a reference signal.

10. The device of claim 9 , wherein the control circuit comprises:

a comparator configured to compare the output signal with the reference signal to generate the control signal to an output node; and

an output capacitor coupled to the output node.

11. A method for generating a duty cycle ratio for a clock, comprising:

generating, by a converter, an output signal to an output terminal according to an input signal;

generating a single control signal based on the output signal and a reference signal; and

generating, by a corrector, at least one current according to the control signal, and transmitting the at least one current to the output terminal without transmitting through the converter to correct the duty cycle ratio of the output signal,

wherein the corrector comprises: a first current source circuit directly coupled between the first power source and the output terminal, and configured to generate a first current; and a second current source circuit directly coupled between the output terminal and the second power source, and configured to generate a second current; wherein only the single control signal is transferred to the corrector to control both the first current source circuit and the second current source circuit to generate and directly inject the first current and the second current with different current values to the output terminal to adjust the duty cycle ratio of the first output signal.

12. The method of claim 11 , wherein the corrector and the converter are coupled in parallel with each other and between a first power source and a second power source.

13. The method of claim 11 , wherein generating the control signal comprises:

comparing the output signal with the reference signal to generate the control signal.

14. The method of claim 11 , wherein the second current flows from the output terminal to the second power source.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2016
From: CHIEN, TING-HSU; CHENG, CHIH-WEN; TSAI, JENG-HUNG
To: GLOBAL UNICHIP CORPORATION; TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 039629/0068 →
Priority Claims (1)
CN 2016 1 0351867 · May 25, 2016 · national
Continuity (1)
Related Publication 20170346282A1 · Nov 30, 2017
Cited By (1)
US 12,253,563