Apparatus and methods for power efficient CMOS and BiCMOS transmitters suitable for wireless applications
A silicon based (e.g., SiGe, CMOS, or BiCMOS) transmitter includes an algorithm that strategically segment and pre-distort the input signal according to its power; a reconfigurable power amplifier (PA) having a plurality of PA sections, wherein the plurality of PA sections comprise discrete weighted transistor arrays that are digitally turned OFF or ON according to a magnitude of an input signal; an impedance matching network equipped with a common-mode feedback (CMFB) mechanism configured to reduce common-mode glitches at an output of the PA due to ON/OFF manipulations of the PA segments; and a 1:N transformer, which comprises a capacitive matching engine and a power detector, disposed between the impedance matching network and the reconfigurable linear PA.
1. A silicon-based transmitter, comprising:
a reconfigurable linear power amplifier (PA) having a plurality of PA sections, wherein the plurality of PA sections comprises discrete transistor arrays that can be turned OFF or ON according to a magnitude of an input signal;
a digital signal processor with an algorithm to process the input signal to obtain a control signal that drives the plurality of PA sections and maintains an overall transmitter power gain constant over an entire input signal range;
a set of ON-OFF switchable drivers that control a power of the plurality of PA sections according to the control signal;
an impedance matching network equipped with a bank of capacitors to reduce PA output impedance variations due to turning ON or OFF of the plurality of PA sections;
a common-mode feedback (CMFB) mechanism configured to reduce common-mode variations and glitches at an output of the PA due to turning ON or OFF of the plurality of PA sections; and
a capacitive matching engine comprising a set of compensating capacitors configured to maintain a substantially constant output node capacitance.
2. The silicon-based transmitter according to claim 1 , wherein the control signal used to control the reconfigurable linear PA is generated from the input signal that is segmented and pre-processed in the digital signal processor.
3. The silicon-based transmitter according to claim 1 , wherein the plurality of PA sections are controlled by a set of switchable PA drivers.
4. The silicon-based transmitter according to claim 1 , wherein the CMFB mechanism comprises a power detector that samples a power level at the output of the PA, wherein the power level is used to adjust a transmitter output power through an RF programmable gain amplifier (PGA).
5. The silicon-based transmitter according to claim 1 , further comprising a 1:N transformer disposed between the impedance matching network and the reconfigurable linear PA.
6. The silicon-based transmitter, wherein the silicon-based transmitter is a SiGe, CMOS, or BiCMOS transmitter.
7. A method for radio frequency transmission using the silicon-based transmitter of claim 1 , comprising:
processing an input signal, using the digital signal processor, to obtain the control signal;
based on the control signal, regulating the set of ON-OFF switchable drivers to control the plurality of PA sections;
adjusting the PA output impedance using the impedance matching network;
maintaining the output node capacitance substantially constant using the capacitive matching engine; and
reducing the common-mode glitches at the output of the PA using the common-mode feedback mechanism.