Semiconductor apparatus including a power gating circuit

1. A semiconductor apparatus comprising:

a logic circuit;

a power gating circuit comprising a first gating transistor configured to apply a first supply voltage to the logic circuit based on an operation mode of the semiconductor apparatus;

a characteristic monitoring circuit configured to generate characteristic information by monitoring a characteristic of the logic circuit, wherein the characteristic of the logic circuit comprises at least one of process variation and temperature variation; and

a power gating control circuit configured to supply a first back bias voltage to the first gating transistor based on the characteristic information.

2. The semiconductor apparatus of claim 1 , wherein the characteristic monitoring circuit comprises:

a pulse generator configured to receive a clock signal and generate a level signal and reference signal;

a delay line comprising a plurality of delay units configured by replicating the logic circuit, wherein the plurality of delay units sequentially delays the level signal; and

a characteristic information generator configured to generate the characteristic information from outputs of the plurality of delay units based on the reference signal.

3. The semiconductor apparatus of claim 2 , wherein the characteristic information generator comprises:

a plurality of flip flops coupled to the outputs of the corresponding delay units among the plurality of delay units, and configured to receive the outputs of the corresponding delay units based on the reference signal, respectively; and

an encoder configured to generate the characteristic information by encoding output signals of the plurality of flip-flops.

4. The semiconductor apparatus of claim 2 ,

wherein the delay amount of the delay line is changed depending on a temperature at which the logic circuit is operated at; and

wherein the delay amount of the delay line is changed depending on a process variation of the logic circuit based on a reference variation.

5. The semiconductor apparatus of claim 1 , wherein the power gating control circuit comprises:

a register configured to receive and store the characteristic information;

a controller configured to provide an enable signal to the characteristic information monitoring circuit, and to generate a voltage code based on the characteristic information stored in the register; and

a voltage generator configured to generate the first back bias voltage based on the voltage code.

6. The semiconductor apparatus of claim 5 , wherein the register stores the characteristic information as fast mode characteristic information when the semiconductor apparatus is operated at a first frequency, and stores the characteristic information as slow mode characteristic information when the semiconductor apparatus is operated at a second frequency lower than the first frequency.

7. The semiconductor apparatus of claim 6 , wherein the controller receives the fast mode characteristic information when the semiconductor apparatus is operated at the first frequency, and receives the slow mode characteristic information when the semiconductor apparatus is operated at the second frequency.

8. The semiconductor apparatus of claim 5 , wherein the enable signal is periodically enabled when and after the semiconductor apparatus is booted up, and enables the characteristic monitoring circuit.

9. The semiconductor apparatus of claim 5 , wherein the power gating circuit further comprises a second gating transistor configured to apply a second supply voltage to the logic circuit based on the operation mode of the semiconductor apparatus, and

the power gating control circuit supplies a second back bias voltage to the second gating transistor based on the characteristic information.

10. The semiconductor apparatus of claim 9 , wherein the voltage generator further generates the second back bias voltage based on the voltage code.

11. A semiconductor apparatus comprising:

a first logic circuit;

a first power gating circuit comprising a first gating transistor configured to apply a first supply voltage to the first logic circuit based on an operation mode of the semiconductor apparatus;

a second logic circuit;

a second power gating circuit comprising a second gating transistor configured to apply the first supply voltage to the second logic circuit based on the operation mode of the semiconductor apparatus;

a characteristic monitoring circuit configured to generate first characteristic information by monitoring a characteristic of the first logic circuit, and to generate second characteristic information by monitoring a characteristic of the second logic circuit, wherein the characteristics of the first and second logic circuits comprise at least one of process variation and temperature variation; and

a power gating control circuit configured to provide a first back bias voltage to the first gating transistor based on the first characteristic information, and to provide a second back bias voltage to the second gating transistor based on the second characteristic information.

12. The semiconductor apparatus of claim 11 , wherein the characteristic monitoring circuit comprises:

a pulse generator configured to receive a clock signal and generate a level signal and reference signal;

a first delay line comprising a plurality of delay units configured by replicating the first logic circuit, wherein the plurality of delay units sequentially delay the level signal;

a first characteristic information generator configured to generate the first characteristic information from outputs of the plurality of delay units of the first delay line, based on the reference signal;

a second delay line comprising a plurality of delay units configured by replicating the second logic circuit, wherein the plurality of delay units sequentially delay the level signal; and

a second characteristic information generator configured to generate the second characteristic information from outputs of the plurality of delay units of the second delay line.

13. The semiconductor apparatus of claim 12 ,

wherein the delay amount of the first delay line is changed depending on a temperature at which the first logic circuit is operated at;

wherein the delay amount of the first delay line is changed depending on a process variation of the first logic circuit based on a reference variation;

wherein the delay amount of the second delay line is changed depending on a temperature at which the second logic circuit is operated at; and

wherein the delay amount of the second delay line is changed depending on a process variation of the second logic circuit based on a reference variation.

14. The semiconductor apparatus of claim 11 , wherein the power gating control circuit comprises:

a register configured to receive and to store the first and second characteristic information;

a controller configured to provide an enable signal to the characteristic monitoring circuit, to generate a first voltage code based on the first characteristic information stored in the register, and to generate a second voltage code based on the second characteristic information stored in the register; and

a voltage generator configured to generate the first back bias voltage based on the first voltage code, and to generate the second back bias voltage based on the second voltage code.

15. The semiconductor apparatus of claim 14 , wherein the register stores the first and second characteristic information as first and second fast mode characteristic information when the semiconductor apparatus is operated at a first frequency, and stores the first and second characteristic information as first and second slow mode characteristic information when the semiconductor apparatus is operated at a second frequency lower than the first frequency.

16. The semiconductor apparatus of claim 15 , wherein the controller receives the first and second fast mode characteristic information when the semiconductor apparatus is operated at the first frequency, and receives the first and second slow mode characteristic information when the semiconductor apparatus is operated at the second frequency.

17. The semiconductor apparatus of claim 15 , wherein the enable signal is periodically enabled when and after the semiconductor apparatus is booted up, and enables the characteristic monitoring circuit.

18. The semiconductor apparatus of claim 15 , wherein the first power gating circuit further comprises a third gating transistor configured to supply a second supply voltage to the first logic circuit based on the operation mode of the semiconductor apparatus, and

the voltage generator generates a third back bias voltage to provide to the third gating transistor, based on the first characteristic information.

19. The semiconductor apparatus of claim 15 , wherein the second power gating circuit further comprises a fourth gating transistor configured to supply a second supply voltage to the second logic circuit based on the operation mode of the semiconductor apparatus, and

the voltage generator generates a fourth back bias voltage to provide to the fourth gating transistor, based on the second characteristic information.